Anant Singh

According to our database, Anant Singh authored at least 12 papers between 2006 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

A 16nm 140-fJ/b/dB Dual-Mode ENRZ/NRZ Serial Data Transceiver with Dynamic Voltage Scaling.

Armin Tajalli, Cosimo Aprile, Milad Ataei, Rolf Beerwerth, Dario Carneli, Maik Fuhs, Kiarash Gharibdoust, Ali Hormati, James Hudner, Victor Perrin, Amin Shokrollahi, Richard Simpson, Andrew Stewart, David Stauffer, Giuseppe Surace, Roger Ulrich, Patrick Urban, Mark Venneborger, Anant Singh

Proceedings of the IEEE Custom Integrated Circuits Conference, 2025

2024

FineZip : Pushing the Limits of Large Language Models for Practical Lossless Text Compression.

Fazal Mittu, Yihuan Bu, Akshat Gupta, Ashok Devireddy, Alp Eren Ozdarendeli, Anant Singh, Gopala Anumanchipalli

CoRR, 2024

2023

Decoding Emotions: A comprehensive Multilingual Study of Speech Models for Speech Emotion Recognition.

Anant Singh, Akshat Gupta

CoRR, 2023

Have Large Language Models Developed a Personality?: Applicability of Self-Assessment Tests in Measuring Personality in LLMs.

Xiaoyang Song, Akshat Gupta, Kiyan Mohebbizadeh, Shujie Hu, Anant Singh

CoRR, 2023

2020

A 1.02-pJ/b 20.83-Gb/s/Wire USR Transceiver Using CNRZ-5 in 16-nm FinFET.

Armin Tajalli, Mani Bastani Parizi, Dario Albino Carnelli, Chen Cao, Kiarash Gharibdoust, Davide Gorret, Amit Gupta, Christopher Hall, Ahmed Hassanin, Klaas L. Hofstra, Brian Holden, Ali Hormati, John Keay, Yohann Mogentale, Victor Perrin, John Phillips, Sumathi Raparthy, Amin Shokrollahi, David Stauffer, Richard Simpson, Andrew Stewart, Giuseppe Surace, Omid Talebi Amiri, Emanuele Truffa, Anton Tschank, Roger Ulrich, Christoph Walter, Anant Singh

IEEE J. Solid State Circuits, 2020

Physical Insights into Phosphorene Transistor Degradation Under Exposure to Atmospheric Conditions and Electrical Stress.

Jeevesh Kumar, Ansh, Asha Yadav, Anant Singh, Andrew Naclerio, Dmitri N. Zakharov, Piran Kidambi, Mayank Shrivastava

Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Short-Reach and Pin-Efficient Interfaces Using Correlated NRZ.

Armin Tajalli, Mani Bastani Parizi, Dario Albino Carnelli, Chen Cao, Kiarash Gharibdoust, Amit Gupta, Ahmed Hassanin, Klaas L. Hofstra, Brian Holden, Ali Hormati, John Keay, Amin Shokrollahi, David Stauffer, Richard Simpson, Andrew Stewart, Giuseppe Surace, Omid Talebi Amiri, Anton Tschank, Roger Ulrich, Christoph Walter, Anant Singh

Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2019

A 1.02pJ/b 417Gb/s/mm USR Link in 16nm FinFET.

Armin Tajalli, Mani Bastani Parizi, Dario Albino Carnelli, Chen Cao, John Fox, Kiarash Gharibdoust, Davide Gorret, Amit Gupta, Christopher Hall, Ahmed Hassanin, Klaas L. Hofstra, Brian Holden, Ali Hormati, John Keay, Yohann Mogentale, G. Paul, Victor Perrin, John Phillips, Sumathi Raparthy, Amin Shokrollahi, David Stauffer, Richard Simpson, Andrew Stewart, Giuseppe Surace, Omid Talebi Amiri, Emanuele Truffa, Anton Tschank, Roger Ulrich, Christoph Walter, Anant Singh

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

2016

10.1 A pin-efficient 20.83Gb/s/wire 0.94pJ/bit forwarded clock CNRZ-5-coded SerDes up to 12mm for MCM packages in 28nm CMOS.

Amin Shokrollahi, Dario Albino Carnelli, John Fox, Klaas L. Hofstra, Brian Holden, Ali Hormati, Peter Hunt, Margaret Johnston, John Keay, Sergio Pesenti, Richard Simpson, David Stauffer, Andrew Stewart, Giuseppe Surace, Armin Tajalli, Omid Talebi Amiri, Anton Tschank, Roger Ulrich, Christoph Walter, Fabio Licciardello, Yohann Mogentale, Anant Singh

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2014

26.3 A pin- and power-efficient low-latency 8-to-12Gb/s/wire 8b8w-coded SerDes link for high-loss channels in 40nm technology.

Anant Singh, Dario Albino Carnelli, Altay Falay, Klaas L. Hofstra, Fabio Licciardello, Kia Salimi, Hugo Santos, Amin Shokrollahi, Roger Ulrich, Christoph Walter, John Fox, Peter Hunt, John Keay, Richard Simpson, Andrew Stewart, Giuseppe Surace, Harm S. Cronie

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2009

A 2ns-read-latency 4Mb embedded floating-body memory macro in 45nm SOI technology.

Anant Singh, Michael Ciraula, Don Weiss, John J. Wuu, Philippe Bauser, Paul de Champs, Hamid Daghighian, David E. Fisch, Philippe Graber, Michel Bron

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2006

Z-RAM® ultra-dense memory for 90nm and below.

David E. Fisch, Anant Singh, Greg Popov

Proceedings of the 2006 IEEE Hot Chips 18 Symposium (HCS), 2006