André Sülflow

Nat. Comput., 2015

Diagnostic Tests and Diagnosis for Delay Faults Using Path Segmentation.

[BibT_eX]

[DOI]

Tino Flenker

Proceedings of the 24th IEEE Asian Test Symposium, 2015

2014

Latency Analysis for Sequential Circuits.

[BibT_eX]

[DOI]

Alexander Finder

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

2013

Automated design debugging in a testbench-based verification environment.

[BibT_eX]

[DOI]

Mehdi Dehbashi

Microprocess. Microsystems, 2013

Incorporating User Preferences in Many-Objective Optimization using Relation Epsilon-Preferred.

[BibT_eX]

[DOI]

Nicole Drechsler

Proceedings of the IJCCI 2013, 2013

2012

FoREnSiC- An Automatic Debugging Environment for C Programs.

[BibT_eX]

[DOI]

Proceedings of the Hardware and Software: Verification and Testing, 2012

2011

Effective Robustness Analysis Using Bounded Model Checking Techniques.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

2010

WoLFram - a word level framework for formal verification and its application.

[BibT_eX]

[DOI]

PhD thesis, 2010

Automatische formale Verifikation der Fehlertoleranz von Schaltkreisen (Automated Formal Verification of Fault Tolerance for Circuits).

[BibT_eX]

[DOI]

it Inf. Technol., 2010

Towards Unifying Localization and Explanation for Automated Debugging.

[BibT_eX]

[DOI]

Proceedings of the 11th International Workshop on Microprocessor Test and Verification, 2010

Using QBF to increase accuracy of SAT-based debugging.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Automatic Fault Localization for Programmable Logic Controllers.

[BibT_eX]

[DOI]

Proceedings of the FORMS/FORMAT 2010, 2010

Bounded Fault Tolerance Checking.

[BibT_eX]

Proceedings of the 2010 Forum on specification & Design Languages, 2010

RobuCheck: A Robustness Checker for Digital Circuits.

[BibT_eX]

[DOI]

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2009

WoLFram- A Word Level Framework for Formal Verification.

[BibT_eX]

[DOI]

Proceedings of the Twentienth IEEE/IFIP International Symposium on Rapid System Prototyping, 2009

Evaluation of Cardinality Constraints on SMT-Based Debugging.

[BibT_eX]

[DOI]

Proceedings of the ISMVL 2009, 2009

Robustness Check for Multiple Faults Using Formal Techniques.

[BibT_eX]

[DOI]

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

Increasing the accuracy of SAT-based debugging.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

SWORD - Module-based SAT Solving.

[BibT_eX]

[DOI]

Proceedings of the Algorithms and Applications for Next Generation SAT Solvers, 08.11., 2009

Computing bounds for fault tolerance using formal techniques.

[BibT_eX]

[DOI]

Proceedings of the 46th Design Automation Conference, 2009

2008

Debugging Design Errors by Using Unsatisfiable Cores.

[BibT_eX]

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2008

Using unsatisfiable cores to debug multiple design errors.

[BibT_eX]

[DOI]

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

2007

Verbesserte SAT basierte Fehlerdiagnose durch Widerspruchanalyse.

[BibT_eX]

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2007

Modeling a Fully Scalable Reed-Solomon Encoder/Decoder over GF(p^{m}) in SystemC.

[BibT_eX]

[DOI]

Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007

Robust Multi-Objective Optimization in High Dimensional Spaces.

[BibT_eX]

[DOI]

Nicole Drechsler