Aneesh Balakrishnan

According to our database, Aneesh Balakrishnan authored at least 12 papers between 2019 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2021

On Antagonism Between Side-Channel Security and Soft-Error Reliability in BNN Inference Engines.

Xinhui Lai, Thomas Lange, Aneesh Balakrishnan, Dan Alexandrescu, Maksim Jenihhin

Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021

Gate-Level Graph Representation Learning: A Step Towards the Improved Stuck-at Faults Analysis.

Aneesh Balakrishnan, Dan Alexandrescu, Maksim Jenihhin, Thomas Lange, Maximilien Glorieux

Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

Modeling Soft-Error Reliability Under Variability.

Aneesh Balakrishnan, Guilherme Cardoso Medeiros, Cemil Cem Gürsoy, Said Hamdioui, Maksim Jenihhin, Dan Alexandrescu

Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021

2020

Composing Graph Theory and Deep Neural Networks to Evaluate SEU Type Soft Error Effects.

Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Maksim Jenihhin

Proceedings of the 9th Mediterranean Conference on Embedded Computing, 2020

Machine Learning Clustering Techniques for Selective Mitigation of Critical Design Features.

Thomas Lange, Aneesh Balakrishnan, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone

Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020

Enabling Cross-Layer Reliability and Functional Safety Assessment Through ML-Based Compact Models.

Dan Alexandrescu, Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux

Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020

2019

Understanding multidimensional verification: Where functional meets non-functional.

Xinhui Lai, Aneesh Balakrishnan, Thomas Lange, Maksim Jenihhin, Tara Ghasempouri, Jaan Raik, Dan Alexandrescu

Microprocess. Microsystems, 2019

The Validation of Graph Model-Based, Gate Level Low-Dimensional Feature Data for Machine Learning Applications.

Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Maksim Jenihhin

Proceedings of the 2019 IEEE Nordic Circuits and Systems Conference, 2019

Machine Learning to Tackle the Challenges of Transient and Soft Errors in Complex Circuits.

Thomas Lange, Aneesh Balakrishnan, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone

Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

On the Estimation of Complex Circuits Functional Failure Rate by Machine Learning Techniques.

Thomas Lange, Aneesh Balakrishnan, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone

Proceedings of the 49th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2019

Challenges of Reliability Assessment and Enhancement in Autonomous Systems.

Maksim Jenihhin, Matteo Sonza Reorda, Aneesh Balakrishnan, Dan Alexandrescu

Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

Modeling Gate-Level Abstraction Hierarchy Using Graph Convolutional Neural Networks to Predict Functional De-Rating Factors.

Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Maksim Jenihhin

Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2019