Cemil Cem Gürsoy

Orcid: 0000-0001-7529-9092

Affiliations:
  • Yeditepe University, Istanbul, Turkey


According to our database1, Cemil Cem Gürsoy authored at least 12 papers between 2015 and 2022.

Collaborative distances:

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Bibliography

2022
On BTI Aging Rejuvenation in Memory Address Decoders.
Proceedings of the 23rd IEEE Latin American Test Symposium, 2022

2021
Modeling Soft-Error Reliability Under Variability.
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021

2020
A DFT Scheme to Improve Coverage of Hard-to-Detect Faults in FinFET SRAMs.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
High-Level Combined Deterministic and Pseudoexhuastive Test Generation for RISC Processors.
CoRR, 2019

On NBTI-induced Aging Analysis in IEEE 1687 Reconfigurable Scan Networks.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Mixed-level identification of fault redundancy in microprocessors.
Proceedings of the IEEE Latin American Test Symposium, 2019

Software-Based Mitigation for Memory Address Decoder Aging.
Proceedings of the IEEE Latin American Test Symposium, 2019

High-Level Combined Deterministic and Pseudo-exhuastive Test Generation for RISC Processors.
Proceedings of the 24th IEEE European Test Symposium, 2019

New categories of Safe Faults in a processor-based Embedded System.
Proceedings of the 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2019

2016
Erratum to: Speeding Up Logic Locking via Fault Emulation and Dynamic Multiple Fault Injection.
J. Electron. Test., 2016

On optimization of multi-cycle tests for test quality and application time.
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

2015
Speeding Up Logic Locking via Fault Emulation and Dynamic Multiple Fault Injection.
J. Electron. Test., 2015


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