Anna Bernasconi

According to our database1, Anna Bernasconi authored at least 73 papers between 1994 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of two.

Timeline

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Bibliography

2019
Boolean Minimization of Projected Sums of Products via Boolean Relations.
IEEE Trans. Computers, 2019

Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model.
Proceedings of the IEEE Latin American Test Symposium, 2019

Approximate Logic Synthesis by Symmetrization.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Composition of switching lattices for regular and for decomposed functions.
Microprocessors and Microsystems - Embedded Hardware Design, 2018

Enhancing logic synthesis of switching lattices by generalized Shannon decomposition methods.
Microprocessors and Microsystems - Embedded Hardware Design, 2018

Testability of Switching Lattices in the Stuck at Fault Model.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

Two Combinatorial Problems on the Layout of Switching Lattices.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

The Connection Layout in a Lattice of Four-Terminal Switches.
Proceedings of the VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms, 2018

Computing Preimages and Ancestors in Reaction Systems.
Proceedings of the Theory and Practice of Natural Computing - 7th International Conference, 2018

2017
Logic synthesis and testing techniques for switching nano-crossbar arrays.
Microprocessors and Microsystems - Embedded Hardware Design, 2017

Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis.
Proceedings of the Euromicro Conference on Digital System Design, 2017

2016
Index-Resilient Zero-Suppressed BDDs: Definition and Operations.
ACM Trans. Design Autom. Electr. Syst., 2016

Synthesis on switching lattices of Dimension-reducible Boolean functions.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Logic Synthesis for Switching Lattices by Decomposition with P-Circuits.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

2015
On the error resilience of ordered binary decision diagrams.
Theor. Comput. Sci., 2015

Using Flexibility in P-Circuits by Boolean Relations.
IEEE Trans. Computers, 2015

Biconditional-BDD Ordering for Autosymmetric Functions.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Bi-Decomposition Using Boolean Relations.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

2014
Autosymmetric and Dimension Reducible Multiple-Valued Functions.
Multiple-Valued Logic and Soft Computing, 2014

Zero-Suppressed Binary Decision Diagrams Resilient to Index Faults.
Proceedings of the Theoretical Computer Science, 2014

2-SPP Approximate Synthesis for Error Tolerant Applications.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

2013
Compact DSOP and Partial DSOP Forms.
Theory Comput. Syst., 2013

SOP restructuring by exploiting don't cares.
Microprocessors and Microsystems - Embedded Hardware Design, 2013

Minimization of EP-SOPs via Boolean relations.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Error resilient OBDDs.
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

Minimization of P-circuits using Boolean relations.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Synthesis of P-circuits for logic restructuring.
Integration, 2012

Projected Don't Cares.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2011
Dimension-reducible Boolean functions based on affine spaces.
ACM Trans. Design Autom. Electr. Syst., 2011

Autosymmetric Multiple-Valued Functions: Theory and Spectral Characterization.
Proceedings of the 41st IEEE International Symposium on Multiple-Valued Logic, 2011

An approximation algorithm for cofactoring-based synthesis.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

Compact and Testable Circuits for Regular Functions.
Proceedings of the ARCS 2011, 2011

2010
Logic synthesis and testability of D-reducible functions.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

Fun at a Department Store: Data Mining Meets Switching Theory.
Proceedings of the Fun with Algorithms, 5th International Conference, 2010

2009
Logic Minimization and Testability of 2SPP-P-Circuits.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

On decomposing Boolean functions via extended cofactoring.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
The optimization of kEP-SOPs: Computational complexity, approximability and experiments.
ACM Trans. Design Autom. Electr. Syst., 2008

Logic Minimization and Testability of 2-SPP Networks.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Synthesis of Autosymmetric Functions in a New Three-Level Form.
Theory Comput. Syst., 2008

On Projecting Sums of Products.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

2007
An approximation algorithm for fully testable kEP-SOP networks.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Knitting for Fun: A Recursive Sweater.
Proceedings of the Fun with Algorithms, 4th International Conference, 2007

On the Construction of Small Fully Testable Circuits with Low Depth.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

2006
Testability of SPP Three-Level Logic Networks in Static Fault Models.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Exploiting Regularities for Boolean Function Synthesis.
Theory Comput. Syst., 2006

Logic Synthesis of EXOR Projected Sum of Products.
Proceedings of the VLSI-SoC: Research Trends in VLSI and Systems on Chip, 2006

EXOR Projected Sum of Products.
Proceedings of the IFIP VLSI-SoC 2006, 2006

DRedSOP: Synthesis of a New Class of Regular Functions.
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

Efficient minimization of fully testable 2-SPP networks.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2004
Spectral Analysis of Symmetric Threshold Functions.
Multiple-Valued Logic and Soft Computing, 2004

Room allocation: a polynomial subcase of the quadratic assignment problem.
Discrete Applied Mathematics, 2004

2003
Three-level logic minimization based on function regularities.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Complexity of some arithmetic problems for binary polynomials.
Computational Complexity, 2003

Stuck-At-Fault Testability of SPP Three-Level Logic Forms.
Proceedings of the VLSI-SOC: From Systems to Chips, 2003

Testability of SPP Three-Level Logic Networks.
Proceedings of the IFIP VLSI-SoC 2003, 2003

2002
Implicit Test of Regularity for Not Completely Specified Boolean Functions.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

Fast three-level logic minimization based on autosymmetry.
Proceedings of the 39th Design Automation Conference, 2002

2001
A Characterization of Bent Functions in Terms of Strongly Regular Graphs.
IEEE Trans. Computers, 2001

Circuit and Decision Tree Complexity of Some Number Theoretic Problems.
Inf. Comput., 2001

On a hierarchy of Boolean functions hard to compute in constant depth.
Discrete Mathematics & Theoretical Computer Science, 2001

2000
The average sensitivity of square-freeness.
Computational Complexity, 2000

1999
Spectral Analysis of Boolean Functions as a Graph Eigenvalue Problem.
IEEE Trans. Computers, 1999

A Note on the Polynomial Representation of Boolean Functions over GF(2).
Int. J. Found. Comput. Sci., 1999

Hilbert Function and Complexity Lower Bounds for Symmetric Boolean Functions.
Inf. Comput., 1999

Circuit Complexity of Testing Square-Free Numbers.
Proceedings of the STACS 99, 1999

On the Average Sensitivity of Testing Square-Free Numbers.
Proceedings of the Computing and Combinatorics, 5th Annual International Conference, 1999

1998
Circuit and Decision Tree Complexity of Some Number Theoretic Problems
Universität Trier, Mathematik/Informatik, Forschungsbericht, 1998

Circuit Complexity of Testing Square-Free Numbers
Electronic Colloquium on Computational Complexity (ECCC), 1998

Combinatorial Properties of Classes of Functions Hard to Compute in Constant Depth.
Proceedings of the Computing and Combinatorics, 4th Annual International Conference, 1998

1997
On the Complexity of Balanced Boolean Functions.
Proceedings of the Algorithms and Complexity, Third Italian Conference, 1997

1996
Sensitivity vs. Block Sensitivity (an Average-Case Study).
Inf. Process. Lett., 1996

1994
Measures of Boolean Function Complexity Based on Harmonic Analysis.
Proceedings of the Algorithms and Complexity, Second Italian Conference, 1994


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