Arul Sendhil

According to our database1, Arul Sendhil authored at least 6 papers between 2011 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2015
A Novel CKE-ODT-CSN Encoding Scheme in DDR Memory Interface.
Proceedings of the 28th International Conference on VLSI Design, 2015

2013
A Novel Scheme to Reset through Clock.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

At-speed I/O Test for Fast Vref Optimization in High Speed Single-ended Memory Systems.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

2012
A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface.
IEEE J. Solid State Circuits, 2012

2011
Self-Calibrating Equalizer for Optimal Jitter Performance Using On-chip Eye Monitoring.
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

An output structure for a bi-modal 6.4-Gbps GDDR5 and 2.4-Gbps DDR3 compatible memory interface.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011


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