Arunkumar Vijayan

Orcid: 0000-0002-6915-6084

Affiliations:
  • Karlsruhe Institute of Technology, Germany


According to our database1, Arunkumar Vijayan authored at least 12 papers between 2015 and 2022.

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Bibliography

2022
A Data-driven Approach for Fault Detection in the Alternator Unit of Automotive Systems.
Proceedings of the IEEE European Test Symposium, 2022

2020
Runtime Identification of Hardware Trojans by Feature Analysis on Gate-Level Unstructured Data and Anomaly Detection.
ACM Trans. Design Autom. Electr. Syst., 2020

Dynamic Faults based Hardware Trojan Design in STT-MRAM.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Runtime Monitoring for Dependable Hardware Design.
PhD thesis, 2019

2018
Workload-Aware Static Aging Monitoring and Mitigation of Timing-Critical Flip-Flops.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Fine-Grained Aging-Induced Delay Prediction Based on the Monitoring of Run-Time Stress.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Online Soft-Error Vulnerability Estimation for Memory Arrays and Logic Cores.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

2017
Workload-aware static aging monitoring of timing-critical flip-flops.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Online soft-error vulnerability estimation for memory arrays.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

2015
Self-awareness and self-learning for resiliency in real-time systems.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

Fine-Grained Aging Prediction Based on the Monitoring of Run-Time Stress Using DfT Infrastructure.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Re-using BIST for circuit aging monitoring.
Proceedings of the 20th IEEE European Test Symposium, 2015


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