Abhishek Koneru

Orcid: 0000-0002-3808-7303

According to our database1, Abhishek Koneru authored at least 17 papers between 2015 and 2022.

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Bibliography

2022
Disruptive Changes in Field Equation Modeling: A Simple Interface for Wafer Scale Engines.
CoRR, 2022

2020
An Interlayer Interconnect BIST and Diagnosis Solution for Monolithic 3-D ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

2019
A Design-for-Test Solution Based on Dedicated Test Layers and Test Scheduling for Monolithic 3-D Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Reliable Power Delivery and Analysis of Power-Supply Noise During Testing in Monolithic 3D ICs.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019

Test and Design-for-Testability Solutions for Monolithic 3D Integrated Circuits.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

2018
Fine-Grained Aging-Induced Delay Prediction Based on the Monitoring of Run-Time Stress.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

An inter-layer interconnect BIST solution for monolithic 3D ICs.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Power-Supply Noise Analysis for Monolithic 3D ICs Using Electrical and Thermal Co-Simulation.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2017
Impact of Electrostatic Coupling and Wafer-Bonding Defects on Delay Testing of Monolithic 3D Integrated Circuits.
ACM J. Emerg. Technol. Comput. Syst., 2017

A Design-for-Test Solution for Monolithic 3D Integrated Circuits.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Design automation and testing of monolithic 3D ICs: Opportunities, challenges, and solutions: (Invited paper).
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

2016
Online soft-error vulnerability estimation for memory arrays.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Analysis of electrostatic coupling in monolithic 3D integrated circuits and its impact on delay testing.
Proceedings of the 21th IEEE European Test Symposium, 2016

2015
Accurate Analysis and Prediction of Enterprise Service-Level Performance.
ACM Trans. Design Autom. Electr. Syst., 2015

Self-awareness and self-learning for resiliency in real-time systems.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

Fine-Grained Aging Prediction Based on the Monitoring of Run-Time Stress Using DfT Infrastructure.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Re-using BIST for circuit aging monitoring.
Proceedings of the 20th IEEE European Test Symposium, 2015


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