Fabian Oboril

According to our database1, Fabian Oboril authored at least 60 papers between 2010 and 2020.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
Achieving Energy Efficiency for Near-Threshold Circuits Through Postfabrication Calibration and Adaptation.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Integration of Formal Safety Models on System Level Using the Example of Responsibility Sensitive Safety and CARLA Driving Simulator.
Proceedings of the Computer Safety, Reliability, and Security. SAFECOMP 2020 Workshops, 2020

2019
Precise localization relative to 3D Automated Driving map using the Decentralized Kalman filter with Feedback.
CoRR, 2019

Towards Standardization of AV Safety: C++ Library for Responsibility Sensitive Safety.
Proceedings of the 2019 IEEE Intelligent Vehicles Symposium, 2019

Object-level Perception Sharing Among Connected Vehicles.
Proceedings of the 2019 IEEE Intelligent Transportation Systems Conference, 2019

2018
An Experimental Evaluation and Analysis of Transient Voltage Fluctuations in FPGAs.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Workload-Aware Static Aging Monitoring and Mitigation of Timing-Critical Flip-Flops.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

VAET-STT: Variation Aware STT-MRAM Analysis and Design Space Exploration Tool.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

A cross-layer adaptive approach for performance and power optimization in STT-MRAM.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Design of Defect and Fault-Tolerant Nonvolatile Spintronic Flip-Flops.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Contemporary CMOS aging mitigation techniques: Survey, taxonomy, and methods.
Integr., 2017

Leveraging Systematic Unidirectional Error-Detecting Codes for fast STT-MRAM cache.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017

Architecting SOT-RAM Based GPU Register File.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Post-fabrication calibration of Near-Threshold circuits for energy efficiency.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Voltage drop-based fault attacks on FPGAs using valid bitstreams.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Energy Efficient Scientific Computing on FPGAs using OpenCL.
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

Exploiting STT-MRAM for approximate computing.
Proceedings of the 22nd IEEE European Test Symposium, 2017

VAET-STT: A variation aware estimator tool for STT-MRAM based memories.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Workload-aware static aging monitoring of timing-critical flip-flops.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Self-Timed Read and Write Operations in STT-MRAM.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Ultra-Fast and High-Reliability SOT-MRAM: From Cache Replacement to Normally-Off Computing.
IEEE Trans. Multi Scale Comput. Syst., 2016

Fault tolerant approximate computing using emerging non-volatile spintronic memories.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Instruction cache aging mitigation through Instruction Set Encoding.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Normally-OFF STT-MRAM Cache with Zero-Byte Compression for Energy Efficient Last-Level Caches.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

Maximizing Energy Efficiency in NTC by Variation-Aware Microprocessor Pipeline Optimization.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

A cross-layer approach for resiliency and energy efficiency in near threshold computing.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Low-Power Multi-Port Memory Architecture based on Spin Orbit Torque Magnetic Devices.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Analysis of transient voltage fluctuations in FPGAs.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

Cross-Layer Approaches for an Aging-Aware Design Space Exploration for Microprocessors.
Proceedings of the Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems, 2016

A cross-layer analysis of Soft Error, aging and process variation in Near Threshold Computing.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Fault Tolerant Non-Volatile spintronic flip-flop.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Non-Volatile Non-Shadow flip-flop using Spin Orbit Torque for efficient normally-off computing.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Cross-Layer Approaches for an Aging-Aware Design of Nanoscale Microprocessors.
PhD thesis, 2015

Exploiting Instruction Set Encoding for Aging-Aware Microprocessor Design.
ACM Trans. Design Autom. Electr. Syst., 2015

Evaluation of Hybrid Memory Technologies Using SOT-MRAM for On-Chip Cache Hierarchy.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Application-aware cross-layer reliability analysis and optimization.
it Inf. Technol., 2015

Cross-layer approaches for an aging-aware design of nanoscale microprocessors: Dissertation summary: IEEE TTTC E.J. McCluskey doctoral thesis award competition finalist.
Proceedings of the 2015 IEEE International Test Conference, 2015

Cross-layer resilient system design flow.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Deadspace-aware Power/Ground TSV planning in 3D floorplanning.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

Improving reliability, performance, and energy efficiency of STT-MRAM with dynamic write latency.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Protecting caches against multi-bit errors using embedded erasure coding.
Proceedings of the 20th IEEE European Test Symposium, 2015

High-resolution online power monitoring for modern microprocessors.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Stress-aware P/G TSV planning in 3D-ICs.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Aging mitigation in memory arrays using self-controlled bit-flipping technique.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Aging-Aware Design of Microprocessor Instruction Pipelines.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Read disturb fault detection in STT-MRAM.
Proceedings of the 2014 International Test Conference, 2014

Avoiding unnecessary write operations in STT-MRAM for low power implementation.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

P/G TSV planning for IR-drop reduction in 3D-ICs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Asynchronous Asymmetrical Write Termination (AAWT) for a low power STT-MRAM.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

ArISE: Aging-aware instruction set encoding for lifetime improvement.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

Architectural aspects in design and analysis of SOT-based memories.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Negative Bias Temperature Instability-Aware Instruction Scheduling: A Cross-Layer Approach.
J. Low Power Electron., 2013

A-SOFT-AES: Self-adaptive software-implemented fault-tolerance for AES.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

Aging-aware logic synthesis.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

MTTF-balanced pipeline design.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Reducing wearout in embedded processors using proactive fine-grain dynamic runtime adaptation.
Proceedings of the 17th IEEE European Test Symposium, 2012

ExtraTime: Modeling and analysis of wearout due to transistor aging at microarchitecture-level.
Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks, 2012

Reducing NBTI-induced processor wearout by exploiting the timing slack of instructions.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

2011
Numerical Defect Correction as an Algorithm-Based Fault Tolerance Technique for Iterative Solvers.
Proceedings of the 17th IEEE Pacific Rim International Symposium on Dependable Computing, 2011

2010
Parallel 3D Multigrid Methods on the STI Cell BE Architecture.
Proceedings of the Facing the Multicore-Challenge, 2010


  Loading...