Sarath Mohanachandran Nair

According to our database1, Sarath Mohanachandran Nair authored at least 17 papers between 2017 and 2020.

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Bibliography

2020
Mitigating Read Failures in STT-MRAM.
Proceedings of the 38th IEEE VLSI Test Symposium, 2020

Special Session - Emerging Memristor Based Memory and CIM Architecture: Test, Repair and Yield Analysis.
Proceedings of the 38th IEEE VLSI Test Symposium, 2020

Physics based modeling of bimodal electromigration failure distributions and variation analysis for VLSI interconnects.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Defect Characterization and Test Generation for Spintronic-based Compute-In-Memory.
Proceedings of the IEEE European Test Symposium, 2020

A Universal Spintronic Technology based on Multifunctional Standardized Stack.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Dynamic Faults based Hardware Trojan Design in STT-MRAM.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
A Comprehensive Framework for Parametric Failure Modeling and Yield Analysis of STT-MRAM.
IEEE Trans. Very Large Scale Integr. Syst., 2019

A Spintronics Memory PUF for Resilience Against Cloning Counterfeit.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Variation-Aware Physics-Based Electromigration Modeling and Experimental Calibration for VLSI Interconnects.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

Variation-aware Fault Modeling and Test Generation for STT-MRAM.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

2018
VAET-STT: Variation Aware STT-MRAM Analysis and Design Space Exploration Tool.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Defect injection, Fault Modeling and Test Algorithm Generation Methodology for STT-MRAM.
Proceedings of the IEEE International Test Conference, 2018

Using multifunctional standardized stack as universal spintronic technology for IoT.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Parametric failure modeling and yield analysis for STT-MRAM.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Process variation and temperature aware adaptive scrubbing for retention failures in STT-MRAM.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
GREAT: HeteroGeneous IntegRated Magnetic tEchnology Using Multifunctional Standardized sTack.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

VAET-STT: A variation aware estimator tool for STT-MRAM based memories.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017


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