Berkin Akin

Orcid: 0000-0001-6908-5581

According to our database1, Berkin Akin authored at least 27 papers between 2012 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2022
Towards the Co-design of Neural Networks and Accelerators.
Proceedings of Machine Learning and Systems 2022, 2022

An Evaluation of Edge TPU Accelerators for Convolutional Neural Networks.
Proceedings of the IEEE International Symposium on Workload Characterization, 2022

Searching for Efficient Neural Architectures for On-Device ML on Edge TPUs.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops, 2022

2021
Mitigating Edge Machine Learning Inference Bottlenecks: An Empirical Study on Accelerating Google Edge Models.
CoRR, 2021

Rethinking Co-design of Neural Architectures and Hardware Accelerators.
CoRR, 2021

Apollo: Transferable Architecture Exploration.
CoRR, 2021

MobileDets: Searching for Object Detection Architectures for Mobile Accelerators.
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2021

Discovering Multi-Hardware Mobile Models via Architecture Search.
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition Workshops, 2021

Google Neural Network Models for Edge Devices: Analyzing and Mitigating Machine Learning Inference Bottlenecks.
Proceedings of the 30th International Conference on Parallel Architectures and Compilation Techniques, 2021

2020
MobileDets: Searching for Object Detection Architectures for Mobile Accelerators.
CoRR, 2020

Accelerator-aware Neural Network Design using AutoML.
CoRR, 2020

2019
A Case For Asymmetric Processing in Memory.
IEEE Comput. Archit. Lett., 2019

ZCOMP: Reducing DNN Cross-Layer Memory Footprint Using Vector Extensions.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

Memory system characterization of deep learning workloads.
Proceedings of the International Symposium on Memory Systems, 2019

2018
Dynamic fine-grained sparse memory accesses.
Proceedings of the International Symposium on Memory Systems, 2018

A case for hardware-supported sub-cache line accesses.
Proceedings of the 14th International Workshop on Data Management on New Hardware, 2018

2016
FFTs with Near-Optimal Memory Access Through Block Data Layouts: Algorithm, Architecture and Design Automation.
J. Signal Process. Syst., 2016

HAMLeT Architecture for Parallel Data Reorganization in Memory.
IEEE Micro, 2016

2015
Enabling portable energy efficiency with memory accelerated library.
Proceedings of the 48th International Symposium on Microarchitecture, 2015

Data reorganization in memory using 3D-stacked DRAM.
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

2014
FFTS with near-optimal memory access through block data layouts.
Proceedings of the IEEE International Conference on Acoustics, 2014

Algorithm/hardware co-optimized SAR image reconstruction with 3D-stacked logic in memory.
Proceedings of the IEEE High Performance Extreme Computing Conference, 2014

HAMLeT: Hardware accelerated memory layout transform within 3D-stacked DRAM.
Proceedings of the IEEE High Performance Extreme Computing Conference, 2014

Understanding the design space of DRAM-optimized hardware FFT accelerators.
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014

2013
A 3D-stacked logic-in-memory accelerator for application-specific data intensive computing.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2012
Algorithm and architecture optimization for large size two dimensional discrete fourier transform (abstract only).
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

Memory Bandwidth Efficient Two-Dimensional Fast Fourier Transform Algorithm and Implementation for Large Problem Sizes.
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012


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