Satrajit Chatterjee

CoRR, 2022

On the Generalization Mystery in Deep Learning.

[BibT_eX]

[DOI]

CoRR, 2022

TIGRIS: An Informed Sampling-based Algorithm for Informative Path Planning.

[BibT_eX]

[DOI]

Brady G. Moon

Sebastian A. Scherer

Proceedings of the IEEE/RSJ International Conference on Intelligent Robots and Systems, 2022

2021

Enabling Binary Neural Network Training on the Edge.

[BibT_eX]

[DOI]

George A. Constantinides

CoRR, 2021

Apollo: Transferable Architecture Exploration.

[BibT_eX]

[DOI]

CoRR, 2021

Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

Making Coherence Out of Nothing At All: Measuring the Evolution of Gradient Alignment.

[BibT_eX]

[DOI]

CoRR, 2020

Explaining Memorization and Generalization: A Large-Scale Study with Coherent Gradients.

[BibT_eX]

[DOI]

Shankar Krishnan

CoRR, 2020

Circuit-Based Intrinsic Methods to Detect Overfitting.

[BibT_eX]

[DOI]

Proceedings of the 37th International Conference on Machine Learning, 2020

Coherent Gradients: An Approach to Understanding Generalization in Gradient Descent-based Optimization.

[BibT_eX]

[DOI]

Proceedings of the 8th International Conference on Learning Representations, 2020

2018

Learning and Memorization.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Machine Learning, 2018

2012

Automatic generation of inductive invariants from high-level microarchitectural models of communication fabrics.

[BibT_eX]

[DOI]

Formal Methods Syst. Des., 2012

xMAS: Quick Formal Modeling of Communication Fabrics to Enable Verification.

[BibT_eX]

[DOI]

Ümit Y. Ogras

IEEE Des. Test Comput., 2012

2011

Verifying Deadlock-Freedom of Communication Fabrics.

[BibT_eX]

[DOI]

Alexander Gotmanov

Proceedings of the Verification, Model Checking, and Abstract Interpretation, 2011

System interconnect design exploration for embedded MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Workshop on System Level Interconnect Prediction, 2011

2010

Physical-Aware Link Allocation and Route Assignment for Chip Multiprocessing.

[BibT_eX]

[DOI]

Proceedings of the NOCS 2010, 2010

Quick formal modeling of communication fabrics to enable verification.

[BibT_eX]

[DOI]

Ümit Y. Ogras

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010

2008

Boolean factoring and decomposition of logic networks.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

2007

Improvements to Technology Mapping for LUT-Based FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Combinational and sequential mapping with priority cuts.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

On Resolution Proofs for Combinational Equivalence.

[BibT_eX]

[DOI]

Proceedings of the 44th Design Automation Conference, 2007

2006

Reducing Structural Bias in Technology Mapping.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Improvements to combinational equivalence checking.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Factor cuts.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

DAG-aware AIG rewriting a fresh look at combinational logic synthesis.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

2004

A new incremental placement algorithm and its application to congestion-aware divisor extraction.

[BibT_eX]

[DOI]