Satrajit Chatterjee

Orcid: 0000-0001-8135-8378

According to our database1, Satrajit Chatterjee authored at least 27 papers between 2004 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Enabling Binary Neural Network Training on the Edge.
ACM Trans. Embed. Comput. Syst., November, 2023

2022
A Closer Look at Hardware-Friendly Weight Quantization.
CoRR, 2022

On the Generalization Mystery in Deep Learning.
CoRR, 2022

TIGRIS: An Informed Sampling-based Algorithm for Informative Path Planning.
Proceedings of the IEEE/RSJ International Conference on Intelligent Robots and Systems, 2022

2021
Enabling Binary Neural Network Training on the Edge.
CoRR, 2021

Apollo: Transferable Architecture Exploration.
CoRR, 2021


2020
Making Coherence Out of Nothing At All: Measuring the Evolution of Gradient Alignment.
CoRR, 2020

Explaining Memorization and Generalization: A Large-Scale Study with Coherent Gradients.
CoRR, 2020

Circuit-Based Intrinsic Methods to Detect Overfitting.
Proceedings of the 37th International Conference on Machine Learning, 2020

Coherent Gradients: An Approach to Understanding Generalization in Gradient Descent-based Optimization.
Proceedings of the 8th International Conference on Learning Representations, 2020

2018
Learning and Memorization.
Proceedings of the 6th International Conference on Learning Representations, 2018

2012
Automatic generation of inductive invariants from high-level microarchitectural models of communication fabrics.
Formal Methods Syst. Des., 2012

xMAS: Quick Formal Modeling of Communication Fabrics to Enable Verification.
IEEE Des. Test Comput., 2012

2011
Verifying Deadlock-Freedom of Communication Fabrics.
Proceedings of the Verification, Model Checking, and Abstract Interpretation, 2011

System interconnect design exploration for embedded MPSoCs.
Proceedings of the 2011 International Workshop on System Level Interconnect Prediction, 2011

2010
Physical-Aware Link Allocation and Route Assignment for Chip Multiprocessing.
Proceedings of the NOCS 2010, 2010

Quick formal modeling of communication fabrics to enable verification.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010

2008
Boolean factoring and decomposition of logic networks.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

2007
Improvements to Technology Mapping for LUT-Based FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Combinational and sequential mapping with priority cuts.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

On Resolution Proofs for Combinational Equivalence.
Proceedings of the 44th Design Automation Conference, 2007

2006
Reducing Structural Bias in Technology Mapping.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Improvements to combinational equivalence checking.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Factor cuts.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

DAG-aware AIG rewriting a fresh look at combinational logic synthesis.
Proceedings of the 43rd Design Automation Conference, 2006

2004
A new incremental placement algorithm and its application to congestion-aware divisor extraction.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004


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