Bo Jiao

According to our database, Bo Jiao authored at least 11 papers between 2021 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

37.4 SHINSAI: A 586mm² Reusable Active TSV Interposer with Programmable Interconnect Fabric and 512Mb 3D Underdeck Memory.

Bo Jiao, Haozhe Zhu, Yuman Zeng, Yongjiang Li, Jie Liao, Siyao Jia, Mochen Tian, Zexing Chen, Jundong Zhu, Dexin Wen, Yan Wang, Yu Wang, Jian Xu, Feng Wang, Jun Tao, Chixiao Chen, Qi Liu, Ming Liu

Proceedings of the IEEE International Solid-State Circuits Conference, 2025

EIGEN: Enabling Efficient 3DIC Interconnect with Heterogeneous Dual-Layer Network-on-Active-Interposer.

Siyao Jia, Bo Jiao, Haozhe Zhu, Chixiao Chen, Qi Liu, Ming Liu

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2025

Hydra: Harnessing Expert Popularity for Efficient Mixture-of-Expert Inference on Chiplet System.

Siqi He, Haozhe Zhu, Jiapei Zheng, Lizhou Wu, Bo Jiao, Qi Liu, Xiaoyang Zeng, Chixiao Chen

Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

2024

FPIA: Communication-Aware Multi-Chiplet Integration With Field-Programmable Interconnect Fabric on Reusable Silicon Interposer.

Bo Jiao, Lei Xu, Xinyu Yu, Haitao Yang, Haozhe Zhu, Yu Wang, Jundong Zhu, Dexin Wen, Lingli Wang, Jun Tao, Chixiao Chen, Yinhe Han, Qi Liu, Ninghui Sun, Ming Liu

IEEE Trans. Circuits Syst. I Regul. Pap., September, 2024

A 28nm 76.25TOPS/W RRAM/SRAM-Collaborative CIM Fine-Tuning Accelerator with RRAM-Endurance/Latency-Aware Weight Allocation for CNN and Transformer.

Chen Mu, Zhirui Huang, Hao Jiang, Jie Liao, Bo Jiao, Yuliang Zhou, Haozhe Zhu, Jianguo Yang, Qi Liu, Chixiao Chen

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024

2023

A Scalable Die-to-Die Interconnect with Replay and Repair Schemes for 2.5D/3D Integration.

Jie Liao, Bo Jiao, Jinshan Zhang, Shiwei Liu, Hao Jiang, Jun Tao, Wenning Jiang, Qi Liu, Lihua Zhang, Haozhe Zhu, Chixiao Chen

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022

COMB-MCM: Computing-on-Memory-Boundary NN Processor with Bipolar Bitwise Sparsity Optimization for Scalable Multi-Chiplet-Module Edge Machine Learning.

Haozhe Zhu, Bo Jiao, Jinshan Zhang, Xinru Jia, Yunzhengmao Wang, Tianchan Guan, Shengcheng Wang, Dimin Niu, Hongzhong Zheng, Chixiao Chen, Mingyu Wang, Lihua Zhang, Xiaoyang Zeng, Qi Liu, Yuan Xie, Ming Liu

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

CA-SpaceNet: Counterfactual Analysis for 6D Pose Estimation in Space.

Shunli Wang, Shuaibing Wang, Bo Jiao, Dingkang Yang, Liuzhen Su, Peng Zhai, Chixiao Chen, Lihua Zhang

Proceedings of the IEEE/RSJ International Conference on Intelligent Robots and Systems, 2022

2021

ALPINE: An Agile Processing-in-Memory Macro Compilation Framework.

Jinshan Zhang, Bo Jiao, Yunzhengmao Wang, Haozhe Zhu, Lihua Zhang, Chixiao Chen

Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

Computing Utilization Enhancement for Chiplet-based Homogeneous Processing-in-Memory Deep Learning Processors.

Bo Jiao, Haozhe Zhu, Jinshan Zhang, Shunli Wang, Xiaoyang Kang, Lihua Zhang, Mingyu Wang, Chixiao Chen

Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

A 0.57-GOPS/DSP Object Detection PIM Accelerator on FPGA.

Bo Jiao, Jinshan Zhang, Yuanyuan Xie, Shunli Wang, Haozhe Zhu, Xiaoyang Kang, Zhiyan Dong, Lihua Zhang, Chixiao Chen

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021