Shengcheng Wang

Orcid: 0000-0001-6939-4552

According to our database1, Shengcheng Wang authored at least 14 papers between 2014 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
COMB-MCM: Computing-on-Memory-Boundary NN Processor with Bipolar Bitwise Sparsity Optimization for Scalable Multi-Chiplet-Module Edge Machine Learning.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2019
Defect Clustering-Aware Spare-TSV Allocation in 3-D ICs for Yield Enhancement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

2018
Reliable Design of Three-Dimensional Integrated Circuits
PhD thesis, 2018

Recovery-Aware Proactive TSV Repair for Electromigration Lifetime Enhancement in 3-D ICs.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Multicast Testing of Interposer-Based 2.5D ICs: Test-Architecture Design and Test Scheduling.
ACM Trans. Design Autom. Electr. Syst., 2018

2017
Electromigration-Aware Local-Via Allocation in Power/Ground TSVs of 3-D ICs.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Leveraging recovery effect to reduce electromigration degradation in power/ground TSV.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Recovery-aware proactive TSV repair for electromigration in 3D ICs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Thermal-aware TSV repair for electromigration in 3D ICs.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Multicast Test Architecture and Test Scheduling for Interposer-Based 2.5D ICs.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015
Deadspace-aware Power/Ground TSV planning in 3D floorplanning.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

Defect Clustering-Aware Spare-TSV Allocation for 3D ICs.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Stress-aware P/G TSV planning in 3D-ICs.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
P/G TSV planning for IR-drop reduction in 3D-ICs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014


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