Chandra Tirumurti
  According to our database1,
  Chandra Tirumurti
  authored at least 20 papers
  between 2003 and 2017.
  
  
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
  2017
    IEEE Trans. Very Large Scale Integr. Syst., 2017
    
  
  2016
Low-Cost and High-Reduction Approaches for Power Droop during Launch-On-Shift Scan-Based Logic BIST.
    
  
    IEEE Trans. Computers, 2016
    
  
  2015
    IEEE Trans. Computers, 2015
    
  
  2014
    Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014
    
  
  2013
    J. Electron. Test., 2013
    
  
    Proceedings of the 18th IEEE European Test Symposium, 2013
    
  
  2012
    IEEE Trans. Very Large Scale Integr. Syst., 2012
    
  
Global Signal Vulnerability (GSV) Analysis for Selective State Element Hardening in Modern Microprocessors.
    
  
    IEEE Trans. Computers, 2012
    
  
  2011
Instruction-Level Impact Analysis of Low-Level Faults in a Modern Microprocessor Controller.
    
  
    IEEE Trans. Computers, 2011
    
  
Workload-Cognizant Concurrent Error Detection in the Scheduler of a Modern Microprocessor.
    
  
    IEEE Trans. Computers, 2011
    
  
    Proceedings of the 16th European Test Symposium, 2011
    
  
  2010
Low cost and low intrusive approach to test on-line the scheduler of high performance microprocessors.
    
  
    Proceedings of the 7th Conference on Computing Frontiers, 2010
    
  
  2009
Instruction-Level Impact Comparison of RT- vs. Gate-Level Faults in a Modern Microprocessor Controller.
    
  
    Proceedings of the 27th IEEE VLSI Test Symposium, 2009
    
  
    Proceedings of the 27th IEEE VLSI Test Symposium, 2009
    
  
    Proceedings of the 27th International Conference on Computer Design, 2009
    
  
  2008
Design and Evaluation of a Timestamp-Based Concurrent Error Detection Method (CED) in a Modern Microprocessor Controller.
    
  
    Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008
    
  
  2007
    Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007
    
  
  2005
    IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
    
  
  2004
A Modeling Approach for Addressing Power Supply Switching Noise Related Failures of Integrated Circuit.
    
  
    Proceedings of the 2004 Design, 2004
    
  
  2003