Chandra Tirumurti

According to our database1, Chandra Tirumurti authored at least 20 papers between 2003 and 2017.

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Bibliography

2017
Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST.
IEEE Trans. Very Large Scale Integr. Syst., 2017

2016
Low-Cost and High-Reduction Approaches for Power Droop during Launch-On-Shift Scan-Based Logic BIST.
IEEE Trans. Computers, 2016

2015
Revisiting Vulnerability Analysis in Modern Microprocessors.
IEEE Trans. Computers, 2015

2014
Power droop reduction during Launch-On-Shift scan-based logic BIST.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

2013
On the Impact of Performance Faults in Modern Microprocessors.
J. Electron. Test., 2013

Novel approach to reduce power droop during scan-based logic BIST.
Proceedings of the 18th IEEE European Test Symposium, 2013

2012
Functional Test-Sequence Grading at Register-Transfer Level.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Global Signal Vulnerability (GSV) Analysis for Selective State Element Hardening in Modern Microprocessors.
IEEE Trans. Computers, 2012

2011
Instruction-Level Impact Analysis of Low-Level Faults in a Modern Microprocessor Controller.
IEEE Trans. Computers, 2011

Workload-Cognizant Concurrent Error Detection in the Scheduler of a Modern Microprocessor.
IEEE Trans. Computers, 2011

AVF Analysis Acceleration via Hierarchical Fault Pruning.
Proceedings of the 16th European Test Symposium, 2011

2010
Low cost and low intrusive approach to test on-line the scheduler of high performance microprocessors.
Proceedings of the 7th Conference on Computing Frontiers, 2010

2009
Instruction-Level Impact Comparison of RT- vs. Gate-Level Faults in a Modern Microprocessor Controller.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009

RT-Level Deviation-Based Grading of Functional Test Sequences.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009

Impact analysis of performance faults in modern microprocessors.
Proceedings of the 27th International Conference on Computer Design, 2009

2008
Design and Evaluation of a Timestamp-Based Concurrent Error Detection Method (CED) in a Modern Microprocessor Controller.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

2007
Estimating Error Propagation Probabilities with Bounded Variances.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

2005
On modeling crosstalk faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

2004
A Modeling Approach for Addressing Power Supply Switching Noise Related Failures of Integrated Circuit.
Proceedings of the 2004 Design, 2004

2003
On Modeling Cross-Talk Faults.
Proceedings of the 2003 Design, 2003


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