Chang Wu

This page is a disambiguation page, it actually contains mutiple papers from persons of the same or a similar name.

Bibliography

2025

Physiological Signal-Driven QoE Optimization for Wireless Virtual Reality Transmission.

[BibT_eX]

[DOI]

CoRR, August, 2025

Topology-Aware Microservice Architecture in Edge Networks: Deployment Optimization and Implementation.

[BibT_eX]

[DOI]

IEEE Trans. Mob. Comput., July, 2025

A 1998-Mpixels/s 75-pJ/pixel Slice-Alternated Display Stream Compression Encoder.

[BibT_eX]

[DOI]

Zekun Zhang

Chang Wu

IEEE Trans. Circuits Syst. II Express Briefs, July, 2025

Streaming 360° VR Video With Statistical QoS Provisioning in mmWave Networks From Delay and Rate Perspectives.

[BibT_eX]

[DOI]

IEEE Trans. Wirel. Commun., June, 2025

Algorithmic-Level Design Partitioning for Latency Minimization in Multi-Chip and Multi-Die Systems.

[BibT_eX]

[DOI]

Cheng Zuo

Chang Wu

ACM Trans. Reconfigurable Technol. Syst., June, 2025

FPGA Technology Mapping With Adaptive Gate Decomposition.

[BibT_eX]

[DOI]

Chang Wu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2025

CFP: Low-overhead Profiling-based Intra-operator Parallelism Generation by Preserving Communication-Free Structures.

[BibT_eX]

[DOI]

CoRR, April, 2025

DMSA: A Decentralized Microservice Architecture for Edge Networks.

[BibT_eX]

[DOI]

CoRR, January, 2025

Radical or Incremental? The Effects of Green Innovation on the Supply Base Stability of Logistics Service Providers.

[BibT_eX]

[DOI]

IEEE Trans. Engineering Management, 2025

A lightweight frame buffer compression codec for memory-efficient applications.

[BibT_eX]

[DOI]

Zekun Zhang

Chang Wu

Microelectron. J., 2025

L3former: Enhanced multi-scale shared Transformer with Local Linear Layer for long-term series forecasting.

[BibT_eX]

[DOI]

Yulin Xia

Chang Wu

Xiaoman Yang

Inf. Fusion, 2025

Integrated STL-DBSCAN algorithm for online hydrological and water quality monitoring data cleaning.

[BibT_eX]

[DOI]

Environ. Model. Softw., 2025

2024

Compact Tunable Reflectionless Phase Shifter With Wide Bandwidth and Low Phase Deviation.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, December, 2024

Cross-Layer Optimization for Statistical QoS Provision in C-RAN With Finite-Length Coding.

[BibT_eX]

[DOI]

IEEE Trans. Commun., June, 2024

Statistical QoS Provision in Business-Centric Networks.

[BibT_eX]

[DOI]

Chang Wu

Yuang Chen

Hancheng Lu

CoRR, 2024

Performance Optimization in RSMA-assisted Uplink xURLLC IIoT Networks with Statistical QoS Provisioning.

[BibT_eX]

[DOI]

CoRR, 2024

Strong Nonlinear Capacitive Behavior of a GaN/AlN Varactor Based on Dual-Schottky Junctions With a Cutoff Frequency of 1.5 THz.

[BibT_eX]

[DOI]

IEEE Access, 2024

NetAssistant: Dialogue Based Network Diagnosis in Data Center Networks.

[BibT_eX]

[DOI]

Haopei Wang

Anubhavnidhi Abhashkumar

Proceedings of the 21st USENIX Symposium on Networked Systems Design and Implementation, 2024

2023

Dual-Band Power Divider With Wide Passbands and Wide Harmonic Suppression Utilizing Multi-Mode T-Stub Loaded Slotline Resonators.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, April, 2023

Streaming 360-degree VR Video with Statistical QoS Provisioning in mmWave Networks from Delay and Rate Perspectives.

[BibT_eX]

[DOI]

CoRR, 2023

AQM-based Buffer Delay Guarantee for Congestion Control in 5G Networks.

[BibT_eX]

[DOI]

Proceedings of the IEEE Wireless Communications and Networking Conference, 2023

A Model-driven Early Warning Approach for Transmission Lines Failure under Wind Storms.

[BibT_eX]

[DOI]

Proceedings of the IEEE Sustainable Power and Energy Conference, 2023

Millimeter-Wave AlGaN/GaN MIS-HEMTs with Multiple T-Gate Technology.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Integrated Circuits, 2023

FPGA Technology Mapping with Adaptive Gate Decomposition.

[BibT_eX]

[DOI]

Longfei Fan

Chang Wu

Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023

HierSyn: Fast Synthesis for Large Hierarchical Designs.

[BibT_eX]

[DOI]

Yishan Zhang

Zhiyong Zhang

Chang Wu

Proceedings of the 15th IEEE International Conference on ASIC, 2023

An Efficient Scheduling Algorithm for Stream Computing.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on ASIC, 2023

A General-Purpose Compiler Design for Instruction-Based AI Accelerator Implementation.

[BibT_eX]

[DOI]

Mengxuan Wang

Yuan Linghu

Chang Wu

Proceedings of the 15th IEEE International Conference on ASIC, 2023

2022

An information propagation network dynamic considering multi-platform influences.

[BibT_eX]

[DOI]

Appl. Math. Lett., 2022

Collar Data Synthesis and Its Application for Generating Virtual Collar 3D Novel View from a Single-View.

[BibT_eX]

[DOI]

Proceedings of the IEEE Intl Conf on Parallel & Distributed Processing with Applications, 2022

Real-Time Image Inpainting using PatchMatch Based Two-Generator Adversarial Networks with Optimized Edge Loss Function.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Characterization of Single Event Upsets of Nanoscale FDSOI Circuits Based on the Simulation and Irradiation Results.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Modeling and Analyzing the Multi-Information Network Propagation Dynamics on Hot Events.

[BibT_eX]

[DOI]

Proceedings of the 2022 11th International Conference on Computing and Pattern Recognition, 2022

Hybrid video coding scheme based on VVC and spatio-temporal attention convolution neural network.

[BibT_eX]

[DOI]

Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops, 2022

2021

Dependency Graph-based High-level Synthesis for Maximum Instruction Parallelism.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2021

RSNN: A Software/Hardware Co-Optimized Framework for Sparse Convolutional Neural Networks on FPGAs.

[BibT_eX]

[DOI]

Weijie You

Chang Wu

IEEE Access, 2021

Highly Efficient Modulo Loop Pipeline For High Level Synthesis.

[BibT_eX]

[DOI]

Chang Wu

Jundong Xie

Kexin Wang

Proceedings of the 14th IEEE International Conference on ASIC, 2021

2020

Qualitative analysis of intellectual property forgery in manufacturing enterprises in Industry 4.0 environment.

[BibT_eX]

[DOI]

Chang Wu

Int. J. Technol. Manag., 2020

2019

Design and verification of universal evaluation system for single event effect sensitivity measurement in very-large-scale integrated circuits.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2019

A Reconfigurable Accelerator for Sparse Convolutional Neural Networks.

[BibT_eX]

[DOI]

Weijie You

Chang Wu

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

Highly Efficient Sparse Neural Network Computing: Hardware and Software Solutions.

[BibT_eX]

[DOI]

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

An Efficient Accelerator for Sparse Convolutional Neural Networks.

[BibT_eX]

[DOI]

Weijie You

Chang Wu

Proceedings of the 13th IEEE International Conference on ASIC, 2019

Latency Minimal Scheduling with Maximum Instruction Parallelism.

[BibT_eX]

[DOI]

Zhenghua Gu

Wenqin Wan

Chang Wu

Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018

Resource and data optimization for hardware implementation of deep neural networks targeting FPGA-based edge devices.

[BibT_eX]

[DOI]

Proceedings of the 20th System Level Interconnect Prediction Workshop, 2018

2017

Layout driven FPGA packing algorithm for performance optimization.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2017

Heterogeneous computing for CNN.

[BibT_eX]

[DOI]

Huizi Zhang

Chang Wu

Xiao Hu

Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016

In-place LUT polarity inVersion to mitigate soft errors for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016

2015

Toward Wave Digital Filter based Analog Circuit Emulation on FPGA (Abstract Only).

[BibT_eX]

[DOI]

Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

2014

A List Simulated Annealing Algorithm for Task Scheduling on Network-on-Chip.

[BibT_eX]

[DOI]

J. Comput., 2014

Providing Useful Information for Passengers Based on TTF Model.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Conference on Internet of Things, 2014

2013

The implementation of an improve infrared dim-small target track before detect based on DSP.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Machine Learning and Cybernetics, 2013

2011

An analytical model for Network-on-Chip with finite input buffer.

[BibT_eX]

[DOI]

Jian Wang

Yubai Li

Chang Wu

Frontiers Comput. Sci. China, 2011

2009

Shortest path based simulated annealing algorithm for dynamic facility layout problem under dynamic business environment.

[BibT_eX]

[DOI]

Ming Dong

Chang Wu

Forest Hou

Expert Syst. Appl., 2009

2008

Lottery Router: A Customized Arbitral Priority NOC Router.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer Science and Software Engineering, 2008

A NoC Simulation and Verification Platform Based on SystemC.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer Science and Software Engineering, 2008

2002

Global clustering-based performance-driven circuit partitioning.

[BibT_eX]

[DOI]

Jason Cong

Chang Wu

Proceedings of 2002 International Symposium on Physical Design, 2002

2000

Performance driven multi-level and multiway partitioning with retiming.

[BibT_eX]

[DOI]

Jason Cong

Sung Kyu Lim

Chang Wu

Proceedings of the 37th Conference on Design Automation, 2000

1999

Optimal FPGA mapping and retiming with efficient initial state computation.

[BibT_eX]

[DOI]

Jason Cong

Chang Wu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Cut Ranking and Pruning: Enabling a General and Efficient FPGA Mapping Solution.

[BibT_eX]

[DOI]

Jason Cong

Chang Wu

Yuzheng Ding

Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999

Simultaneous Circuit Partitioning/Clustering with Retiming for Performance Optimization.

[BibT_eX]

[DOI]

Jason Cong

Honching Li

Chang Wu

Proceedings of the 36th Conference on Design Automation, 1999

1998

An efficient algorithm for performance-optimal FPGA technology mapping with retiming.

[BibT_eX]

[DOI]

Jason Cong

Chang Wu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

1997

FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits.

[BibT_eX]

[DOI]

Jason Cong

Chang Wu

Proceedings of the 34st Conference on Design Automation, 1997

1996

An Improved Algorithm for Performance Optimal Technology Mapping with Retiming in LUT-Based FPGA Desig.

[BibT_eX]

[DOI]

Jason Cong

Chang Wu

Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

Chang Wu

Bibliography

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