Chao Zhang

According to our database1, Chao Zhang authored at least 20 papers between 2011 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
Other 

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Bibliography

2018
Shadow Block: Accelerating ORAM Accesses with Data Duplication.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

PM3: Power Modeling and Power Management for Processing-in-Memory.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

2016
Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System.
IEEE Trans. on Circuits and Systems, 2016

Statistical Cache Bypassing for Non-Volatile Memory.
IEEE Trans. Computers, 2016

Accelerate context switch by racetrack-SRAM hybrid cells.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

np-ECC: Nonadjacent position error correction code for racetrack memory.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Exploring Main Memory Design Based on Racetrack Memory Technology.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Pin Tumbler Lock: A shift based encryption mechanism for racetrack memory.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

Performance-centric register file design for GPUs using racetrack memory.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Exploring data placement in racetrack memory based scratchpad memory.
Proceedings of the IEEE Non-Volatile Memory System and Applications Symposium, 2015

Fork path: improving efficiency of ORAM by removing redundant memory accesses.
Proceedings of the 48th International Symposium on Microarchitecture, 2015

Perspectives of racetrack memory based on current-induced domain wall motion: From device to system.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Hi-fi playback: tolerating position errors in shift operations of racetrack memory.
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

From device to system: cross-layer design exploration of racetrack memory.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

An energy efficient backup scheme with low inrush current for nonvolatile SRAM in energy harvesting sensor nodes.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Quantitative modeling of racetrack memory, a tradeoff among area, performance, and power.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
SBAC: a statistics based cache bypassing method for asymmetric-access caches.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

2013
Asymmetric-access aware optimization for STT-RAM caches with process variations.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

An efficient run-time encryption scheme for non-volatile main memory.
Proceedings of the International Conference on Compilers, 2013

2011
Fabrication cost analysis for 2D, 2.5D, and 3D IC designs.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011


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