Chih-Chao Yang
According to our database1,
Chih-Chao Yang authored at least 7 papers
between 2014 and 2025.
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Bibliography
2025
Monolithic Hybrid-3D Standard Cell Library with Sandwiched Inter-Metal Layer for 3D Digital Computation-in-Memory Circuits.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2025
2024
3DIC with Stacked FinFET, Inter-Level Metal, and Field-Size (25×33mm<sup>2</sup>) Single-Crystalline Si on SiO2 by Elevated-Epi.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
Bit-Cost-Scalable 3D DRAM Architecture and Unit Cell First Demonstrated with Integrated Gate-Around and Channel-Around IGZO FETs.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
2018
A Monolithic-3D SRAM Design with Enhanced Robustness and In-Memory Computation Support.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018
2015
Low power algorithm-architecture co-design of fast Independent Component Analysis (FICA) for multi-gas sensor applications.
Proceedings of the VLSI Design, Automation and Test, 2015
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015
2014
Microelectron. Reliab., 2014