Florence Azaïs

According to our database1, Florence Azaïs authored at least 130 papers between 1995 and 2024.

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Bibliography

2024
Utilizing Layout Effects for Analog Logic Locking.
CoRR, 2024

2023
On the Use of the Indirect Test Strategy for Lifetime Performance Monitoring of RF Circuits.
J. Electron. Test., April, 2023

Low-cost digital solution for production test of ZigBee transmitters Special Session "AMS-RF testing".
Proceedings of the 24th IEEE Latin American Test Symposium, 2023

2022
Leveraging Layout-based Effects for Locking Analog ICs.
Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security, 2022

2021
Low-Cost EVM Measurement of ZigBee Transmitters From 1-bit Undersampled Acquisition.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Evaluation of a Two-Tier Adaptive Indirect Test Flow for a Front-End RF Circuit.
J. Electron. Test., 2021

Exploring on-line RF performance monitoring based on the indirect test strategy.
Proceedings of the 22nd IEEE Latin American Test Symposium, 2021

Exploration of a digital-based solution for the generation of 2.4GHz OQPSK test stimuli.
Proceedings of the 26th IEEE European Test Symposium, 2021

Digital test of ZigBee transmitters: Validation in industrial test environment.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
Investigations on the Use of Ensemble Methods for Specification-Oriented Indirect Test of RF Circuits.
J. Electron. Test., 2020

Implementing indirect test of RF circuits without compromising test quality: a practical case study.
Proceedings of the IEEE Latin-American Test Symposium, 2020

Development and Application of Embedded Test Instruments to Digital, Analog/RFs and Secure ICs.
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020

EVM measurement of RF ZigBee transceivers using standard digital ATE.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020

2019
Analytical Models for the Evaluation of Resistive Short Defect Detectability in Presence of Process Variations: Application to 28nm Bulk and FDSOI Technologies.
J. Electron. Test., 2019

Which metrics to use for RF indirect test strategy?
Proceedings of the 16th International Conference on Synthesis, 2019

Use of ensemble methods for indirect test of RF circuits: can it bring benefits?
Proceedings of the IEEE Latin American Test Symposium, 2019

Power Measurement and Spectral Test of ZigBee Transmitters from 1-bit Under-sampled Acquisition.
Proceedings of the 24th IEEE European Test Symposium, 2019

2018
On-chip Generation of Sine-wave Summing Digital Signals: an Analytic Study Considering Implementation Constraints.
J. Electron. Test., 2018

Impact of process variations on the detectability of resistive short defects: Comparative analysis between 28nm Bulk and FDSOI technologies.
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018

Low-cost functional test of a 2.4 GHz OQPSK transmitter using standard digital ATE.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

2017
Resistive Bridging Defect Detection in Bulk, FDSOI and FinFET Technologies.
J. Electron. Test., 2017

Comprehensive Study for Detection of Weak Resistive Open and Short Defects in FDSOI Technology.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Detection of resistive open and short defects in FDSOI under delay-based test: Optimal VDD and body biasing conditions.
Proceedings of the 22nd IEEE European Test Symposium, 2017

2016
Digital Embedded Test Instrument for On-Chip Phase Noise Testing of Analog/RF Integrated Circuits.
J. Circuits Syst. Comput., 2016

SSB Phase Noise Evaluation of Analog/IF Signals on Standard Digital ATE.
J. Electron. Test., 2016

Comparative study of Bulk, FDSOI and FinFET technologies in presence of a resistive short defect.
Proceedings of the 17th Latin-American Test Symposium, 2016

Impact of VT and Body-Biasing on Resistive Short Detection in 28nm UTBB FDSOI - LVT and RVT Configurations.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

2015
Efficiency evaluation of analog/RF alternate test: Comparative study of indirect measurement selection strategies.
Microelectron. J., 2015

Phase Noise Testing of Analog/IF Signals Using Digital ATE: A New Post-Processing Algorithm for Extended Measurement Range.
J. Electron. Test., 2015

Special session: Hot topics: Statistical test methods.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

A digital technique for the evaluation of SSB phase noise of analog/RF signals.
Proceedings of the 16th Latin-American Test Symposium, 2015

A Framework for Efficient Implementation of Analog/RF Alternate Test with Model Redundancy.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Toward Adaptation of ADCs to Operating Conditions through On-chip Correction.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

A new technique for low-cost phase noise production testing from 1-bit signal acquisition.
Proceedings of the 20th IEEE European Test Symposium, 2015

Analog test: Why still "à la mode" after more than 25 years of research?
Proceedings of the 20th IEEE European Test Symposium, 2015

Embedded Test Instrument for On-Chip Phase Noise Evaluation of Analog/IF Signals.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

2014
Enhancing confidence in indirect analog/RF testing against the lack of correlation between regular parameters and indirect measurements.
Microelectron. J., 2014

Testing for gate oxide short defects using the detectability interval paradigm.
it Inf. Technol., 2014

Study of Low-Cost Electrical Test Strategies for Post-Silicon Yield Improvement of MEMS Convective Accelerometers.
J. Electron. Test., 2014

Phase noise measurement on IF analog signals using standard digital ATE resources.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

Evaluation of indirect measurement selection strategies in the context of analog/RF alternate testing.
Proceedings of the 15th Latin American Test Workshop, 2014

Low-cost phase noise testing of complex RF ICs using standard digital ATE.
Proceedings of the 2014 International Test Conference, 2014

Solutions for the self-adaptation of communicating systems in operation.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

New implementions of predictive alternate analog/RF test with augmented model redundancy.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
A novel implementation of the histogram-based technique for measurement of INL of LUT-based correction of ADC.
Microelectron. J., 2013

Accurate and efficient analytical electrical model of antenna for NFC applications.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

Pre-characterization procedure for a mixed mode simulation of IR-drop induced delays.
Proceedings of the 14th Latin American Test Workshop, 2013

Implementing model redundancy in predictive alternate test to improve test confidence.
Proceedings of the 18th IEEE European Test Symposium, 2013

MIRID: Mixed-Mode IR-Drop Induced Delay Simulator.
Proceedings of the 22nd Asian Test Symposium, 2013

2012
Smart selection of indirect parameters for DC-based alternate RF IC testing.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Low-cost SNR estimation of analog signals using standard digital automated test equipment (ATE).
Proceedings of the 10th IEEE International NEWCAS Conference, 2012

Design-for-manufacturability of MEMS convective accelerometers through adaptive electrical calibration strategy.
Proceedings of the 13th Latin American Test Workshop, 2012

Making predictive analog/RF alternate test strategy independent of training set size.
Proceedings of the 2012 IEEE International Test Conference, 2012

2011
A Behavioral Model of MEMS Convective Accelerometers for the Evaluation of Design and Calibration Strategies at System Level.
J. Electron. Test., 2011

A Level-Crossing Approach for the Analysis of RF Modulated Signals Using Only Digital Test Resources.
J. Electron. Test., 2011

Digital Test Method for Embedded Converters with Unknown-Phase Harmonics.
J. Electron. Test., 2011

Test and calibration of MEMS convective accelerometers with a fully electrical setup.
Proceedings of the 12th Latin American Test Workshop, 2011

An electrical test method for MEMS convective accelerometers: Development and evaluation.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
Study of an Electrical Setup for Capacitive MEMS Accelerometers Test and Calibration.
J. Electron. Test., 2010

Experiments on the analysis of phase/frequency-modulated RF signals using digital tester channels.
Proceedings of the 11th Latin American Test Workshop, 2010

On the use of standard digital ATE for the analysis of RF signals.
Proceedings of the 15th European Test Symposium, 2010

2009
Characterization of the transient behavior of gated/STI diodes and their associated BJT in the CDM time domain.
Microelectron. Reliab., 2009

A multi-converter DFT technique for complex SIP: Concepts and validation.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

An analysis of the timing behavior of CMOS digital blocks under Simultaneous Switching Noise conditions.
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

Exploiting Zero-Crossing for the Analysis of FM Modulated Analog/RF Signals Using Digital ATE.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008
ADC Production Test Technique Using Low-Resolution Arbitrary Waveform Generator.
VLSI Design, 2008

On the Detection of SSN-Induced Logic Errors through On-Chip Monitoring.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

A novel method for test and calibration of capacitive accelerometers with a fully electrical setup.
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

2007
Fully digital test solution for a set of ADCs and DACs embedded in a SIP or SOC.
IET Comput. Digit. Tech., 2007

"Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC.
Proceedings of the 12th European Test Symposium, 2007

Impact of Simultaneous Switching Noise on the Static behavior of Digital CMOS Circuits.
Proceedings of the 16th Asian Test Symposium, 2007

2006
Electro-thermal short pulsed simulation for SOI technology.
Microelectron. Reliab., 2006

Electro-thermal Stimuli for MEMS Testing in FSBM Technology.
J. Electron. Test., 2006

A Novel DFT Technique for Testing Complete Sets of ADCs and DACs in Complex SiPs.
IEEE Des. Test Comput., 2006

2005
A new multi-finger SCR-based structure for efficient on-chip ESD protection.
Microelectron. Reliab., 2005

Built-in self-test of global interconnects of field programmable analog arrays.
Microelectron. J., 2005

Delay Testing Viability of Gate Oxide Short Defects.
J. Comput. Sci. Technol., 2005

Applying the Oscillation Test Strategy to FPAA's Configurable Analog Blocks.
J. Electron. Test., 2005

A Strategy for Optimal Test Point Insertion in Analog Cascaded Filters.
J. Electron. Test., 2005

Efficiency of Optimized Dynamic Test Flows for ADCs: Sensitivity to Specifications.
J. Electron. Test., 2005

Testing the Interconnect Networks and I/O Resources of Field Programmable Analog Arrays.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

On-Chip Electro-Thermal Stimulus Generation for a MEMS-Based Magnetic Field Sensor.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Towards on-line testing of MEMS using electro-thermal excitation.
Proceedings of the 10th European Test Symposium, 2005

2004
Automated Diagnosis and Probing Flow for Fast Fault Localization in IC.
Microelectron. Reliab., 2004

Efficiency of Spectral-Based ADC Test Flows to Detect Static Errors.
J. Electron. Test., 2004

Correlation Between Static and Dynamic Parameters of A-to-D Converters: In the View of a Unique Test Procedure.
J. Electron. Test., 2004

An Approach to the Built-In Self-Test of Field Programmable Analog Arrays.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Testing the Configurable Analog Blocks of Field Programmable Analog Arrays.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Electrically-induced thermal stimuli for MEMS testing.
Proceedings of the 9th European Test Symposium, 2004

Analysis and Attenuation Proposal in Ground Bounce.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003
A-to-D converters static error detection from dynamic parameter measurement.
Microelectron. J., 2003

Modeling the Random Parameters Effects in a Non-Split Model of Gate Oxide Short.
J. Electron. Test., 2003

On-Chip Generation of Ramp and Triangle-Wave Stimuli for ADC BIST.
J. Electron. Test., 2003

Extending IEEE Std. 1149.4 Analog Boundary Modules to Enhance Mixed-Signal Test.
IEEE Des. Test Comput., 2003

An All-Digital DFT Scheme for Testing Catastrophic Faults in PLLs.
IEEE Des. Test Comput., 2003

A New Methodology For ADC Test Flow Optimization.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Delay Testing of MOS Transistor with Gate Oxide Short.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002
Improving Defect Detection in Static-Voltage Testing.
IEEE Des. Test Comput., 2002

Estimating Static Parameters of A-to-D Converters from Spectral Analysis.
Proceedings of the 3rd Latin American Test Workshop, 2002

Modeling gate oxide short defects in CMOS minimum transistors.
Proceedings of the 7th European Test Workshop, 2002

A high accuracy triangle-wave signal generator for on-chip ADC testing.
Proceedings of the 7th European Test Workshop, 2002

European Network for Test Education.
Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

2001
On the detectability of CMOS floating gate transistor faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Optimizing Sinusoidal Histogram Test for Low Cost ADC BIST.
J. Electron. Test., 2001

A Low-Cost BIST Architecture for Linear Histogram Testing of ADCs.
J. Electron. Test., 2001

A Low-Cost Adaptive Ramp Generator for Analog BIST Applications.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Electrical Analysis of Gate Oxide Short in MOS Technologies.
Proceedings of the 2nd Latin American Test Workshop, 2001

On-Chip Generation of High-Quality Ramp Stimulus With Minimal Silicon Area.
Proceedings of the 2nd Latin American Test Workshop, 2001

Boolean and current detection of MOS transistor with gate oxide short.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

On-chip Generator of a Saw-Tooth Test Stimulus for ADC BIST.
Proceedings of the SOC Design Methodologies, 2001

Analog BIST Generator for ADC Testing.
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

Implementation of a linear histogram BIST for ADCs.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000
Combining Functional and Structural Approaches for Switched-Current Circuit Testing.
J. Electron. Test., 2000

Hardware Resource Minimization for Histogram-Based ADC BIST.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

On the Temperature Dependencies of Analog BIST.
Proceedings of the 1st Latin American Test Workshop, 2000

Minimizing the Hardware Overhead of a Histogram-Based BIST Scheme for Analog-to-Digital Converters.
Proceedings of the 1st Latin American Test Workshop, 2000

Towards an ADC BIST scheme using the histogram test technique.
Proceedings of the 5th European Test Workshop, 2000

Reuse of Existing Resources for Analog BIST of a Switch Capacitor Filte.
Proceedings of the 2000 Design, 2000

TI-BIST: a temperature independent analog BIST for switched-capacitor filters.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999
Detection of Defects Using Fault Model Oriented Test Sequences.
J. Electron. Test., 1999

A Successful Distance-Learning Experience for IC Test Education.
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 1999

Optimal conditions for Boolean and current detection of floating gate faults.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

Functional and structural testing of switched-current circuits.
Proceedings of the 4th European Test Workshop, 1999

1998
Design-For-Testability for Switched-Current Circuits.
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

Optimized Implementations of the Multi-Configuration DFT Technique for Analog Circuits.
Proceedings of the 1998 Design, 1998

BISTing Switched-Current Circuits.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

A Methodology and Design for Effective Testing of Voltage-Controlled Oscillators (VCOs.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997
On-chip analog output response compaction.
Proceedings of the European Design and Test Conference, 1997

1996
The multi-configuration: A DFT technique for analog circuits.
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

1995
A design-for-test technique for multistage analog circuits.
Proceedings of the 4th Asian Test Symposium (ATS '95), 1995


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