Hsing-Chung Liang

According to our database1, Hsing-Chung Liang authored at least 10 papers between 1995 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
Wafer-Level Test Path Pattern Recognition and Test Characteristics for Test-Induced Defect Diagnosis.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2009
Improved Representatives for Judging Unrepairability and Deciding Economic Repair Solutions of Memories.
J. Circuits Syst. Comput., 2009

2006
Improved Representatives for Unrepairability Judging and Economic Repair Solutions of Memories.
Proceedings of the 14th IEEE International Workshop on Memory Technology, 2006

2005
Identify unrepairability to speed-up spare allocation for repairing memories.
IEEE Trans. Reliab., 2005

2000
Flip-Flop Selection for Mixed Scan and Reset Design Based on Test Generation and Structure of Sequential Circuits.
J. Inf. Sci. Eng., 2000

1999
An Effective Methodology for Mixed Scan and Reset Design Based on Test Generation and Structure of Sequential Circuits.
Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

1998
Partial Reset and Scan for Flip-Flops Based on States Requirement for Test Generation.
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

1997
Identifying invalid states for sequential circuit test generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

1996
Invalid State Identification for Sequential Circuit Test Generation.
Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

1995
Identifying Untestable Faults in Sequential Circuits.
IEEE Des. Test Comput., 1995


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