According to our database1, Hsing-Chung Liang authored at least 10 papers between 1995 and 2020.
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Wafer-Level Test Path Pattern Recognition and Test Characteristics for Test-Induced Defect Diagnosis.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Improved Representatives for Judging Unrepairability and Deciding Economic Repair Solutions of Memories.
J. Circuits Syst. Comput., 2009
Improved Representatives for Unrepairability Judging and Economic Repair Solutions of Memories.
Proceedings of the 14th IEEE International Workshop on Memory Technology, 2006
IEEE Trans. Reliab., 2005
Flip-Flop Selection for Mixed Scan and Reset Design Based on Test Generation and Structure of Sequential Circuits.
J. Inf. Sci. Eng., 2000
An Effective Methodology for Mixed Scan and Reset Design Based on Test Generation and Structure of Sequential Circuits.
Proceedings of the 8th Asian Test Symposium (ATS '99), 1999
Partial Reset and Scan for Flip-Flops Based on States Requirement for Test Generation.
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997
Proceedings of the 5th Asian Test Symposium (ATS '96), 1996