Ciprian Seiculescu

According to our database¹, Ciprian Seiculescu authored at least 18 papers between 2009 and 2022.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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In proceedings

Article

PhD thesis

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Links

On csauthors.net:

Bibliography

2022

Benchmarking TensorFlow Lite Quantization Algorithms for Deep Neural Networks.

[BibT_eX]

[DOI]

Ioan Lucan Orasan

Ciprian Seiculescu

Catalin-Daniel Caleanu

Proceedings of the 16th IEEE International Symposium on Applied Computational Intelligence and Informatics, 2022

Evaluation of Tracking Algorithms for Contrast Enhanced Ultrasound Imaging Exploration.

[BibT_eX]

[DOI]

Catalin-Daniel Caleanu

Proceedings of the ACSW 2022: Australasian Computer Science Week 2022, Brisbane, Australia, February 14, 2022

2013

Designing best effort networks-on-chip to meet hard latency constraints.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2013

3.5-D integration: A case study.

[BibT_eX]

[DOI]

Shashikanth Bobba

Pierre-Emmanuel Gaillardon

Ciprian Seiculescu

Vasilis F. Pavlidis

Giovanni De Micheli

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012

Design Methods and Tools for Application-Specific Predictable Networks-on-Chip.

[BibT_eX]

[DOI]

Ciprian Seiculescu

PhD thesis, 2012

CCNoC: Specializing On-Chip Interconnects for Energy Efficiency in Cache-Coherent Servers.

[BibT_eX]

[DOI]

Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012

A distributed interleaving scheme for efficient access to WideIO DRAM memory.

[BibT_eX]

[DOI]

Ciprian Seiculescu

Luca Benini

Giovanni De Micheli

Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

2011

3D Network on Chip Topology Synthesis: Designing Custom Topologies for Chip Stacks.

[BibT_eX]

[DOI]

Proceedings of the 3D Integration for NoC-based SoC Architectures, 2011

A DRAM Centric NoC Architecture and Topology Design Approach.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Design and Analysis of NoCs for Low-Power 2D and 3D SoCs.

[BibT_eX]

[DOI]

Proceedings of the Low Power Networks-on-Chip., 2011

2010

Comparative Analysis of NoCs for Two-Dimensional Versus Three-Dimensional SoCs Supporting Multiple Voltage and Frequency Islands.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2010

SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3-D Systems on Chips.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

A method to remove deadlocks in Networks-on-Chips with Wormhole flow control.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

Networks on Chips: from research to products.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

2009

A floorplan-aware interactive tool flow for NoC design and synthesis.

[BibT_eX]

[DOI]

Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

NoC topology synthesis for supporting shutdown of voltage islands in SoCs.

[BibT_eX]

[DOI]

Proceedings of the 46th Design Automation Conference, 2009

Synthesis of networks on chips for 3D systems on chips.

[BibT_eX]

[DOI]

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

Ciprian Seiculescu

Timeline

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On csauthors.net:

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