Victor V. Zyuban

According to our database1, Victor V. Zyuban authored at least 38 papers between 1998 and 2015.

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Bibliography

2015
The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking.
IEEE J. Solid State Circuits, 2015

IBM POWER8 circuit design and energy optimization.
IBM J. Res. Dev., 2015

Session 8 overview: Low-power digital techniques: Energy-efficient digital.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014
5.1 POWER8<sup>TM</sup>: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

The POWER8<sup>TM</sup> processor: Designed for big data, analytics, and cloud environments.
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014

POWER8 design methodology innovations for improving productivity and reducing power.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
IBM POWER7+ design for higher frequency at fixed power.
IBM J. Res. Dev., 2013

Runtime power reduction capability of the IBM POWER7+ chip.
IBM J. Res. Dev., 2013

Power reduction by aggressive synthesis design space exploration.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

Efficient PVT independent abstraction of large IP blocks for hierarchical power analysis.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

2011
POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor.
IEEE J. Solid State Circuits, 2011

2010
The implementation of POWER7<sup>TM</sup>: A highly parallel and scalable multi-core high-end server processor.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

POWER7<sup>TM</sup> local clocking and clocked storage elements.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Power-efficient, reliable microprocessor architectures: modeling and design methods.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

2009
A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR).
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

The opportunity cost of low power design: a case study in circuit tuning.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

2008
A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM Lifetime.
Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008

2007
A Framework for Architecture-Level Lifetime Reliability Modeling.
Proceedings of the 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2007

2005
Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling.
Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005

Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors.
Proceedings of the 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 2005

2004
Integrated Analysis of Power and Performance for Pipelined Microprocessors.
IEEE Trans. Computers, 2004

Microarchitectural techniques for power gating of execution units.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

Design methodology for semi custom processor cores.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

2003
Optimization of scannable latches for low energy.
IEEE Trans. Very Large Scale Integr. Syst., 2003

Balancing hardware intensity in microprocessor pipelines.
IBM J. Res. Dev., 2003

An innovative low-power high-performance programmable signal processor for digital communications.
IBM J. Res. Dev., 2003

Low-power circuits and technology for wireless digital systems.
IBM J. Res. Dev., 2003

2002
Early-Stage Definition of LPX: A Low Power Issue-Execute Processor.
Proceedings of the Power-Aware Computer Systems, Second International Workshop, 2002

Optimizing pipelines for power and performance.
Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002

Unified methodology for resolving power-performance tradeoffs at the microarchitectural and circuit levels.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Low power integrated scan-retention mechanism.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Unified architecture level energy-efficiency metric.
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002

2001
Inherently Lower-Power High-Performance Superscalar Architectures.
IEEE Trans. Computers, 2001

Clocking strategies and scannable latches for low power appliacations.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

2000
Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors.
IEEE Micro, 2000

Optimization of high-performance superscalar architectures for energy efficiency.
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

1999
Application of STD to latch-power estimation.
IEEE Trans. Very Large Scale Integr. Syst., 1999

1998
The energy complexity of register files.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998


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