Victor V. Zyuban
According to our database1,
Victor V. Zyuban
authored at least 38 papers
between 1998 and 2015.
Collaborative distances:
Collaborative distances:
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Bibliography
2015
The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking.
IEEE J. Solid State Circuits, 2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2014
5.1 POWER8<sup>TM</sup>: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
The POWER8<sup>TM</sup> processor: Designed for big data, analytics, and cloud environments.
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
2013
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013
Efficient PVT independent abstraction of large IP blocks for hierarchical power analysis.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013
2011
IEEE J. Solid State Circuits, 2011
2010
The implementation of POWER7<sup>TM</sup>: A highly parallel and scalable multi-core high-end server processor.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010
2009
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009
2008
A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM Lifetime.
Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008
2007
Proceedings of the 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2007
2005
Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling.
Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005
Proceedings of the 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 2005
2004
IEEE Trans. Computers, 2004
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004
2003
IEEE Trans. Very Large Scale Integr. Syst., 2003
An innovative low-power high-performance programmable signal processor for digital communications.
IBM J. Res. Dev., 2003
IBM J. Res. Dev., 2003
2002
Proceedings of the Power-Aware Computer Systems, Second International Workshop, 2002
Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002
Unified methodology for resolving power-performance tradeoffs at the microarchitectural and circuit levels.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002
2001
IEEE Trans. Computers, 2001
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001
2000
Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors.
IEEE Micro, 2000
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000
1999
IEEE Trans. Very Large Scale Integr. Syst., 1999
1998
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998