Davide Conficconi

Orcid: 0000-0002-5834-0812

According to our database1, Davide Conficconi authored at least 30 papers between 2018 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Starlight: A kernel optimizer for GPU processing.
J. Parallel Distributed Comput., May, 2024

NERONE: The Fast Way to Efficiently Execute Your Deep Learning Algorithm at the Edge.
IEEE J. Biomed. Health Informatics, March, 2024

One Automaton to Rule Them All: Beyond Multiple Regular Expressions Execution.
Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization, 2024

2023
Hephaestus: Codesigning and Automating 3D Image Registration on Reconfigurable Architectures.
ACM Trans. Embed. Comput. Syst., October, 2023

Faber: A Hardware/SoftWare Toolchain for Image Registration.
IEEE Trans. Parallel Distributed Syst., 2023

An Energy-Efficient Domain-Specific Architecture for Regular Expressions.
IEEE Trans. Emerg. Top. Comput., 2023

Pushing the Level of Abstraction of Digital System Design: A Survey on How to Program FPGAs.
ACM Comput. Surv., 2023

The Hitchhiker's Guide to FPGA-Accelerated Quantum Error Correction.
Proceedings of the IEEE International Conference on Quantum Computing and Engineering, 2023

YARB: a Methodology to Characterize Regular Expression Matching on Heterogeneous Systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Enabling Efficient Regular Expression Matching at the Edge through Domain-Specific Architectures.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2023

Journal Track Paper ICFPT 2023 : Across Time and Space: Senju's Approach for Scaling Iterative Stencil Loop Accelerators on Single and Multiple FPGAs.
Proceedings of the International Conference on Field Programmable Technology, 2023

Senju: A Framework for the Design of Highly Parallel FPGA-based Iterative Stencil Loop Accelerators.
Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023

On the Design and Characterization of Set Packing Problem on Quantum Annealers.
Proceedings of the 20th IEEE International Conference on Smart Technologies, 2023

A Bird's Eye View on Quantum Computing: Current and Future Trends.
Proceedings of the 20th IEEE International Conference on Smart Technologies, 2023

Co-designing an FPGA-Accelerated Encryption Library With PYNQ: The Pynqrypt Case Study.
Proceedings of the 20th IEEE International Conference on Smart Technologies, 2023

ATHENA: a GPU-based Framework for Biomedical 3D Rigid Image Registration.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2023

2022
On the role of reconfigurable systems in domain-specific computing.
PhD thesis, 2022

Online Learning RTL Synthesis for Automated Design Space Exploration.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2022

On How to Push Efficient Medical Semantic Segmentation to the Edge: the SENECA approach.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2022

Characterizing Molecular Dynamics Simulation on Commodity Platforms.
Proceedings of the IEEE International Symposium on Workload Characterization, 2022

2021

Enhancing the Scalability of Multi-FPGA Stencil Computations via Highly Optimized HDL Components.
ACM Trans. Reconfigurable Technol. Syst., 2021

CICERO: A Domain-Specific Architecture for Efficient Regular Expression Matching.
ACM Trans. Embed. Comput. Syst., 2021

On How FPGAs are Changing the Computer Security Panorama: An Educational Survey.
Proceedings of the 6th IEEE International Forum on Research and Technology for Society and Industry, 2021

Dovado: An Open-Source Design Space Exploration Framework.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2021

A Framework for Customizable FPGA-based Image Registration Accelerators.
Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021

Exploiting Heterogeneous Architectures for Rigid Image Registration.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, BioCAS 2021, 2021

2019
Optimizing Bit-Serial Matrix Multiplication for Reconfigurable Computing.
ACM Trans. Reconfigurable Technol. Syst., 2019

2018
A Parallel, Energy Efficient Hardware Architecture for the merAligner on FPGA Using Chisel HCL.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

TiReX: Tiled Regular eXpression Matching Architecture.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018


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