Giuseppe Natale

According to our database, Giuseppe Natale authored at least 13 papers between 2016 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

Enhancing the Scalability of Multi-FPGA Stencil Computations via Highly Optimized HDL Components.

Enrico Reggiani, Emanuele Del Sozzo, Davide Conficconi, Giuseppe Natale, Carlo Moroni, Marco D. Santambrogio

ACM Trans. Reconfigurable Technol. Syst., 2021

2020

Enabling transparent hardware acceleration on Zynq SoC for scientific computing.

Luca Stornaiuolo, Filippo Carloni, Riccardo Pressiani, Giuseppe Natale, Marco D. Santambrogio, Donatella Sciuto

SIGBED Rev., 2020

2019

On how to design optimized spatial architectures: from iterative stencils to convolutional neural networks.

Giuseppe Natale

PhD thesis, 2019

2018

An FPGA-Based Acceleration Methodology and Performance Model for Iterative Stencils.

Enrico Reggiani, Giuseppe Natale, Carlo Moroni, Marco D. Santambrogio

Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

A Framework with Cloud Integration for CNN Acceleration on FPGA Devices.

Niccolo Raspa, Giuseppe Natale, Marco Bacis, Marco D. Santambrogio

Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

2017

A CAD Open Platform for High Performance Reconfigurable Systems in the EXTRA Project.

Marco Rabozzi, Rolando Brondolin, Giuseppe Natale, Emanuele Del Sozzo, Michael Hübner, Andreas Brokalakis, Catalin Bogdan Ciobanu, Dirk Stroobandt, Marco Domenico Santambrogio

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

On How to Design Dataflow FPGA-Based Accelerators for Convolutional Neural Networks.

Giuseppe Natale, Marco Bacis, Marco Domenico Santambrogio

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

A Pipelined and Scalable Dataflow Implementation of Convolutional Neural Networks on FPGA.

Marco Bacis, Giuseppe Natale, Emanuele Del Sozzo, Marco Domenico Santambrogio

Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

Optimizing streaming stencil time-step designs via FPGA floorplanning.

Marco Rabozzi, Giuseppe Natale, Biagio Festa, Antonio Miele, Marco D. Santambrogio

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

A Feedback-Based Design Space Exploration Subsystem for the Automation of Architectures Synthesis on Proprietary FPGA Toolchains.

Alessandro Pappalardo, Giuseppe Natale, Marco Domenico Santambrogio

Proceedings of the Euromicro Conference on Digital System Design, 2017

Heterogeneous exascale supercomputing: The role of CAD in the exaFPGA project.

Marco Rabozzi, Giuseppe Natale, Emanuele Del Sozzo, Alberto Scolari, Luca Stornaiuolo, Marco D. Santambrogio

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016

On How to Accelerate Iterative Stencil Loops: A Scalable Streaming-Based Approach.

Riccardo Cattaneo, Giuseppe Natale, Carlo Sicignano, Donatella Sciuto, Marco Domenico Santambrogio

ACM Trans. Archit. Code Optim., 2016

A polyhedral model-based framework for dataflow implementation on FPGA devices of iterative stencil loops.

Giuseppe Natale, Giulio Stramondo, Pietro Bressana, Riccardo Cattaneo, Donatella Sciuto, Marco D. Santambrogio

Proceedings of the 35th International Conference on Computer-Aided Design, 2016