Enrico Reggiani

Orcid: 0000-0003-1385-7962

According to our database1, Enrico Reggiani authored at least 17 papers between 2016 and 2023.

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Bibliography

2023
Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications.
ACM Trans. Archit. Code Optim., June, 2023

Mix-GEMM: An efficient HW-SW Architecture for Mixed-Precision Quantized Deep Neural Networks Inference on Edge Devices.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023


Flex-SFU: Accelerating DNN Activation Functions by Non-Uniform Piecewise Approximation.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022
Adaptable Register File Organization for Vector Processors.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022


BiSon-e: a lightweight and high-performance accelerator for narrow integer linear algebra computing on the edge.
Proceedings of the ASPLOS '22: 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Lausanne, Switzerland, 28 February 2022, 2022

2021
Enhancing the Scalability of Multi-FPGA Stencil Computations via Highly Optimized HDL Components.
ACM Trans. Reconfigurable Technol. Syst., 2021

2020
Performance Portable FPGA Design.
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

2019
Pareto Optimal Design Space Exploration for Accelerated CNN on FPGA.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2019

A Case Study for an Accelerated DCNN on FPGA-Based Embedded Distributed System.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2019

2018
An FPGA-Based Acceleration Methodology and Performance Model for Iterative Stencils.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

2017
Pearson Correlation Coefficient Acceleration for Modeling and Mapping of Neural Interconnections.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

A Scalable Dataflow Implementation of Curran's Approximation Algorithm.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

GPU-based computation for brain spatio-temporal networks definition.
Proceedings of the 2017 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2017

From exaflop to exaflow.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
On How to Improve FPGA-Based Systems Design Productivity via SDAccel.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016


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