Deepak Kadetotad
Orcid: 0000-0003-0924-7213
According to our database1,
Deepak Kadetotad
authored at least 23 papers
between 2014 and 2020.
Collaborative distances:
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Bibliography
2020
ECG Authentication Hardware Design With Low-Power Signal Processing and Neural Network Optimization With Low Precision and Structured Compression.
IEEE Trans. Biomed. Circuits Syst., 2020
An 8.93 TOPS/W LSTM Recurrent Neural Network Accelerator Featuring Hierarchical Coarse-Grain Sparsity for On-Device Speech Recognition.
IEEE J. Solid State Circuits, 2020
A Smart Hardware Security Engine Combining Entropy Sources of ECG, HRV, and SRAM PUF for Authentication and Secret Key Generation.
IEEE J. Solid State Circuits, 2020
Proceedings of the Interspeech 2020, 2020
2019
PhD thesis, 2019
A Real-Time 17-Scale Object Detection Accelerator With Adaptive 2000-Stage Classification in 65 nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
A 1.06- $\mu$ W Smart ECG Processor in 65-nm CMOS for Real-Time Biometric Authentication and Personal Cardiac Monitoring.
IEEE J. Solid State Circuits, 2019
ECG Authentication Neural Network Hardware Design with Collective Optimization of Low Precision and Structured Compression.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Neuromorphic Hardware Accelerator for SNN Inference based on STT-RAM Crossbar Arrays.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Joint Optimization of Quantization and Structured Sparsity for Compressed Deep Neural Networks.
Proceedings of the IEEE International Conference on Acoustics, 2019
A 8.93-TOPS/W LSTM Recurrent Neural Network Accelerator Featuring Hierarchical Coarse-Grain Sparsity With All Parameters Stored On-Chip.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
2018
Power, Performance, and Area Benefit of Monolithic 3D ICs for On-Chip Deep Neural Networks Targeting Speech Recognition.
ACM J. Emerg. Technol. Comput. Syst., 2018
2017
Proceedings of the Advances in Computational Intelligence, 2017
Monolithic 3D IC designs for low-power deep neural networks targeting speech recognition.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOS.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
Comprehensive Evaluation of OpenCL-based Convolutional Neural Network Accelerators in Xilinx and Altera FPGAs.
CoRR, 2016
Efficient memory compression in deep neural networks using coarse-grain sparsification for speech applications.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
2015
Parallel Architecture With Resistive Crosspoint Array for Dictionary Learning Acceleration.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015
Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
Face recognition using transform domain feature extraction and PSO-based feature selection.
Appl. Soft Comput., 2014
Neurophysics-inspired parallel architecture with resistive crosspoint array for dictionary learning.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014
Proceedings of the 5th Annual International Conference on Biologically Inspired Cognitive Architectures, 2014