Faaiq G. Waqar

According to our database, Faaiq G. Waqar authored at least 16 papers between 2023 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

Hardware Acceleration of Kolmogorov-Arnold Network (KAN) in Large-Scale Systems.

Wei-Hsing Huang, Jianwei Jia, Yuyao Kong, Faaiq G. Waqar, Tai-Hao Wen, Meng-Fan Chang, Shimeng Yu

IEEE Trans. Very Large Scale Integr. Syst., June, 2026

Optimization and Benchmarking of Monolithically Stackable Gain Cell Memory for Last-Level Cache.

Faaiq G. Waqar, Jungyoun Kwak, Junmo Lee, Omkar Phadke, Minji Shon, MohammadHosein Gholamrezaei, Kevin Skadron, Shimeng Yu

IEEE Trans. Computers, March, 2026

Architecting Long-Context Large Language Model Acceleration With Packing-Prefetch Scheduler and Ultralarge Capacity On-Chip Memories.

Ming-Yen Lee, Faaiq G. Waqar, Hanchen Yang, Muhammed Ahosan Ul Karim, Harsono Simka, Shimeng Yu

IEEE Micro, 2026

Enabling Context-Switchable Monolithic 3D FPGA Design Using Bistable Ferroelectric Inverters.

Faaiq G. Waqar, Matthew Chen, Zifan He, Zishen Wan, Minji Shon, Wei-Hsing Huang, Jason Cong, Shimeng Yu

Proceedings of the 34th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2026

2025

Architecting Long-Context LLM Acceleration with Packing-Prefetch Scheduler and Ultra-Large Capacity On-Chip Memories.

Ming-Yen Lee, Faaiq G. Waqar, Hanchen Yang, Muhammed Ahosan Ul Karim, Harsono Simka, Shimeng Yu

CoRR, August, 2025

3-D Digital Compute-in-Memory Benchmark With A5 CFET Technology: An Extension to Lookup-Table-Based Design.

Junmo Lee, Minji Shon, Faaiq G. Waqar, Shimeng Yu

IEEE Trans. Very Large Scale Integr. Syst., July, 2025

A3D-MoE: Acceleration of Large Language Models with Mixture of Experts via 3D Heterogeneous Integration.

Wei-Hsing Huang, Janak Sharda, Cheng-Jhih Shih, Yuyao Kong, Faaiq G. Waqar, Pin-Jun Chen, Yingyan Lin, Shimeng Yu

CoRR, July, 2025

CMOS+X: Stacking Persistent Embedded Memories based on Oxide Transistors upon GPGPU Platforms.

Faaiq G. Waqar, Ming-Yen Lee, Seongwon Yoon, Seongkwang Lim, Shimeng Yu

CoRR, June, 2025

Optimization and Benchmarking of Monolithically Stackable Gain Cell Memory for Last-Level Cache.

Faaiq G. Waqar, Jungyoun Kwak, Junmo Lee, Minji Shon, MohammadHosein Gholamrezaei, Kevin Skadron, Shimeng Yu

CoRR, March, 2025

Monolithic 3D FPGAs Utilizing Back-End-of-Line Configuration Memories.

Faaiq G. Waqar, Jiahao Zhang, Anni Lu, Zifan He, Jason Cong, Shimeng Yu

CoRR, January, 2025

CMOS+X: Stacking Memories based on Oxide Transistors upon GPGPU Platforms.

Faaiq G. Waqar, Ming-Yen Lee, Seongwon Yoon, Seongkwang Lim, Shimeng Yu

Proceedings of the International Symposium on Memory Systems, 2025

Digital Compute-in-Memory Ising Annealer with Ferroelectric Capacitor-Based nvSRAM for Combinatorial Optimization Problems.

Yuyao Kong, Jianwei Jia, Anni Lu, Faaiq G. Waqar, Yuan-Chun Luo, Hai Li, Ian A. Young, Shimeng Yu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

Radiation-Resilient Amorphous Indium Oxide FEFETs for Embedded Nonvolatile Memory.

Sharadindu Gopal Kirtania, Faaiq G. Waqar, Dyutimoy Chakraborty, Jaewon Shin, Eknath Sarkar, Justin Reiss, Jason Dean Yeager, Douglas E. Wolfe, Shimeng Yu, Suman Datta

Proceedings of the IEEE International Reliability Physics Symposium, 2025

Monolithic 3D FPGA Design and Synthesis with Back-End-of-Line Configuration Memories.

Faaiq G. Waqar, Jiahao Zhang, Anni Lu, Zifan He, Jason Cong, Shimeng Yu

Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

Hardware Acceleration of Kolmogorov-Arnold Network (KAN) for Lightweight Edge Inference.

Wei-Hsing Huang, Jianwei Jia, Yuyao Kong, Faaiq G. Waqar, Tai-Hao Wen, Meng-Fan Chang, Shimeng Yu

Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

2023

A tutorial on the Bayesian statistical approach to inverse problems.

Faaiq G. Waqar, Swati Patel, Cory M. Simon

CoRR, 2023