Gia Bao Thieu

Orcid: 0000-0002-4045-3771

According to our database1, Gia Bao Thieu authored at least 8 papers between 2023 and 2025.

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Bibliography

2025
DCMA: Accelerating Parallel DMA Transfers with a Multi-Port Direct Cached Memory Access in a Massive-Parallel Vector Processor.
ACM Trans. Archit. Code Optim., June, 2025

Design Space Exploration of a Direct Cached Memory Access Controller Optimized for HBM Memory Systems using TAPRE-HBM.
Proceedings of the 2025 Cross-Disciplinary Conference on Memory-Centric Computing (CCMCC), 2025

2024
A Novel Chaining-Based Indirect Addressing Mode in a Vertical Vector Processor.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2024

Multi-Level Prototyping of a Vertical Vector AI Processing System.
Proceedings of the 35th IEEE International Conference on Application-specific Systems, 2024

2023
N<sup>2</sup>V<sup>2</sup>PRO: Neural Network Mapping Framework for a Custom Vector Processor Architecture.
Proceedings of the 13th IEEE International Conference on Consumer Electronics - Berlin, 2023


Radiation Tolerant Reconfigurable Hardware Architecture Design Methodology.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2023

TAPRE-HBM: Trace-Based Processor Rapid Emulation Using HBM on FPGAs.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2023


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