Lennart M. Reimann

According to our database, Lennart M. Reimann authored at least 12 papers between 2020 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

QTFlow: Quantitative Timing-Sensitive Information Flow for Security-Aware Hardware Design on RTL.

Lennart M. Reimann, Anschul Prashar, Chiara Ghinami, Rebecca Pelke, Dominik Sisejkovic, Farhad Merchant, Rainer Leupers

CoRR, 2024

2023

SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors.

Lennart M. Reimann, Jonathan Wiesner, Dominik Sisejkovic, Farhad Merchant, Rainer Leupers

Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023

Automated Information Flow Analysis for Integrated Computing-in-Memory Modules.

Lennart M. Reimann, Felix Staudigl, Rainer Leupers

Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

Quantitative Information Flow for Hardware: Advancing the Attack Landscape.

Lennart M. Reimann, Sarp Erdönmez, Dominik Sisejkovic, Rainer Leupers

Proceedings of the 14th IEEE Latin America Symposium on Circuits and System, 2023

ZuSE Ki-Avf: Application-Specific AI Processor for Intelligent Sensor Signal Processing in Autonomous Driving.

Gia Bao Thieu, Sven Gesper, Guillermo Payá Vayá, Christoph Riggers, Oliver Renke, Till Fiedler, Jakob Marten, Tobias Stuckenberg, Holger Blume, Christian Weis, Lukas Steiner, Chirag Sudarshan, Norbert Wehn, Lennart M. Reimann, Rainer Leupers, Michael Beyer, Daniel Köhler, Alisa Jauch, Jan Micha Borrmann, Setareh Jaberansari, Tim Berthold, Meinolf Blawat, Markus Kock, Gregor Schewior, Jens Benndorf, Frederik Kautz, Hans-Martin Blüthgen, Christian Sauer

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022

Deceptive Logic Locking for Hardware Integrity Protection Against Machine Learning Attacks.

Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann, Rainer Leupers

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2021

Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach.

Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann, Harshit Srivastava, Ahmed Hallawa, Rainer Leupers

ACM J. Emerg. Technol. Comput. Syst., 2021

ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework.

Farhad Merchant, Dominik Sisejkovic, Lennart M. Reimann, Kirthihan Yasotharan, Thomas Grass, Rainer Leupers

Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021

Logic Locking at the Frontiers of Machine Learning: A Survey on Developments and Opportunities.

Dominik Sisejkovic, Lennart M. Reimann, Elmira Moussavi, Farhad Merchant, Rainer Leupers

Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021

QFlow: Quantitative Information Flow for Security-Aware Hardware Design in Verilog.

Lennart M. Reimann, Luca Hanel, Dominik Sisejkovic, Farhad Merchant, Rainer Leupers

Proceedings of the 39th IEEE International Conference on Computer Design, 2021

2020

A secure hardware-software solution based on RISC-V, logic locking and microkernel.

Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann, Rainer Leupers, Massimiliano Giacometti, Sascha Kegreiß

Proceedings of the SCOPES '20: 23rd International Workshop on Software and Compilers for Embedded Systems, 2020

Scaling Logic Locking Schemes to Multi-module Hardware Designs.

Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann, Rainer Leupers, Sascha Kegreiß

Proceedings of the Architecture of Computing Systems - ARCS 2020, 2020