Giorgio Pollaccia

According to our database1, Giorgio Pollaccia authored at least 11 papers between 2001 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
A Low-Cost Burn-In Tester Architecture to Supply Effective Electrical Stress.
IEEE Trans. Computers, May, 2023

2022
Parallel Multithread Analysis of Extremely Large Simulation Traces.
IEEE Access, 2022

2021
Innovative methods for Burn-In related Stress Metrics Computation.
Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021

Accelerated Analysis of Simulation Dumps through Parallelization on Multicore Architectures.
Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021

2019
Effective Screening of Automotive SoCs by Combining Burn-In and System Level Test.
Proceedings of the 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2019

2018
An Evolutionary Algorithm Approach to Stress Program Generation During Burn-In.
J. Low Power Electron., 2018

Adaptive Management Techniques for Optimized Burn-in of Safety-Critical SoC.
J. Electron. Test., 2018

An Optimized Test During Burn-In for Automotive SoC.
IEEE Des. Test, 2018

2017
A comprehensive methodology for stress procedures evaluation and comparison for Burn-In of automotive SoC.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2006
A low-ripple voltage tripler.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2001
Road Signs Recognition Using a Dynamic Pixel Aggregation Technique in the HSV Color Space.
Proceedings of the 11th International Conference on Image Analysis and Processing (ICIAP 2001), 2001


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