Riccardo Cantoro

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

Self-Test Library Generation for In-Field Test of Path Delay Faults.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

A Multilabel Active Learning Framework for Microcontroller Performance Screening.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2023

Automating the Generation of Programs Maximizing the Sustained Switching Activity in Microprocessor units via Evolutionary Techniques.

[BibT_eX]

[DOI]

Microprocess. Microsystems, April, 2023

COVID-19 Detection from Mass Spectra of Exhaled Breath.

[BibT_eX]

[DOI]

Nicolò Bellarmino

Giorgio Bozzini

Josie E. Rodriguez Condia

Francesco Castelletti

Michele Castelluzzo

Carla Ciricugno

Raffaele Correale

Daniela Dalla Gasperina

CoRR, 2023

Functional Testing with STLs: A Step Towards Reliable RISC-V-based HPC Commodity Clusters.

[BibT_eX]

[DOI]

Jacopo Sini

Proceedings of the High Performance Computing, 2023

U-FLEX: Unsupervised Feature Learning with Evolutionary eXploration.

[BibT_eX]

[DOI]

Nicolò Bellarmino

Giovanni Squillero

Proceedings of the Machine Learning, Optimization, and Data Science, 2023

Feature Selection for Cost Reduction In MCU Performance Screening.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE Latin American Test Symposium, 2023

On the integration and hardening of Software Test Libraries in Real-Time Operating Systems.

[BibT_eX]

[DOI]

Francesco Angione

Paolo Bernardi

Nicola Di Gruttola Giardino

Proceedings of the 24th IEEE Latin American Test Symposium, 2023

Automating the Generation of Functional Stress Inducing Stimuli for Burn-In Testing.

[BibT_eX]

[DOI]

Proceedings of the IEEE European Test Symposium, 2023

Semi-Supervised Deep Learning for Microcontroller Performance Screening.

[BibT_eX]

[DOI]

Proceedings of the IEEE European Test Symposium, 2023

A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors.

[BibT_eX]

[DOI]

Proceedings of the IEEE European Test Symposium, 2023

Targeting different defect-oriented fault models in IC testing: an experimental approach.

[BibT_eX]

[DOI]

Proceedings of the 26th Euromicro Conference on Digital System Design, 2023

Evaluating the Impact of Aging on Path-Delay Self-Test Libraries.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

Automatic Identification of Functionally Untestable Cell-Aware Faults in Microprocessors.

[BibT_eX]

[DOI]

Tobias Faller

Iacopo Guglielminetti

Bernd Becker

Proceedings of the 32nd IEEE Asian Test Symposium, 2023

Enabling Inter-Product Transfer Learning on MCU Performance Screening.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE Asian Test Symposium, 2023

2022

Exploiting post-silicon debug hardware to improve the fault coverage of Software Test Libraries.

[BibT_eX]

[DOI]

Proceedings of the 40th IEEE VLSI Test Symposium, 2022

Runtime Test Solution for Adaptive Aging Compensation and Fail Operational Safety mode.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2022

Recent Trends and Perspectives on Defect-Oriented Testing.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022

Microcontroller Performance Screening: Optimizing the Characterization in the Presence of Anomalous and Noisy Data.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022

A comparative overview of ATPG flows targeting traditional and cell-aware fault models.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

Effective techniques for automatically improving the transition delay fault coverage of Self-Test Libraries.

[BibT_eX]

[DOI]

Proceedings of the IEEE European Test Symposium, 2022

Optimized diagnostic strategy for embedded memories of Automotive Systems-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the IEEE European Test Symposium, 2022

Test, Reliability and Functional Safety Trends for Automotive System-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the IEEE European Test Symposium, 2022

Improving the Fault Resilience of Neural Network Applications Through Security Mechanisms.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2022

Using Formal Methods to Support the Development of STLs for GPUs.

[BibT_eX]

[DOI]

Josie E. Rodriguez Condia

Tobias Faller

Bernd Becker

Proceedings of the IEEE 31st Asian Test Symposium, 2022

2021

Towards the Integration of Reliability and Security Mechanisms to Enhance the Fault Resilience of Neural Networks.

[BibT_eX]

[DOI]

IEEE Access, 2021

New Techniques for the Automatic Identification of Uncontrollable Lines in a CPU Core.

[BibT_eX]

[DOI]

Proceedings of the 39th IEEE VLSI Test Symposium, 2021

Self-Test Libraries Analysis for Pipelined Processors Transition Fault Coverage Improvement.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021

Exploiting Active Learning for Microcontroller Performance Prediction.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE European Test Symposium, 2021

Maximizing the Switching Activity of Different Modules Within a Processor Core via Evolutionary Techniques.

[BibT_eX]

[DOI]

Proceedings of the 24th Euromicro Conference on Digital System Design, 2021

Industrial best practice: cases of study by automotive chip- makers.

[BibT_eX]

[DOI]

Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021

Effective SAT-based Solutions for Generating Functional Sequences Maximizing the Sustained Switching Activity in a Pipelined Processor.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE Asian Test Symposium, 2021

2020

Software-Based Self-Test Techniques for Dual-Issue Embedded Processors.

[BibT_eX]

[DOI]

Giovanni Squillero

IEEE Trans. Emerg. Top. Comput., 2020

A Novel Sequence Generation Approach to Diagnose Faults in Reconfigurable Scan Networks.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2020

In-field Functional Test of CAN Bus Controllers.

[BibT_eX]

[DOI]

Sandro Sartoni

Proceedings of the 38th IEEE VLSI Test Symposium, 2020

Evaluating the Code Encryption Effects on Memory Fault Resilience.

[BibT_eX]

[DOI]

Marcello Traiola

Emanuele Valea

Proceedings of the IEEE Latin-American Test Symposium, 2020

Machine Learning based Performance Prediction of Microcontrollers using Speed Monitors.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2020

New Perspectives on Core In-field Path Delay Test.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2020

Determined-Safe Faults Identification: A step towards ISO26262 hardware compliant designs.

[BibT_eX]

[DOI]

Felipe Augusto da Silva

Proceedings of the IEEE European Test Symposium, 2020

Evaluating Data Encryption Effects on the Resilience of an Artificial Neural Network.

[BibT_eX]

[DOI]

Marcello Traiola

Emanuele Valea

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020

2019

An Enhanced Evolutionary Technique for the Generation of Compact Reconfigurable Scan-Network Tests.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2019

A Functional Approach to Test and Debug of IEEE 1687 Reconfigurable Networks.

[BibT_eX]

[DOI]

Michele Portolan

Ernesto Sánchez

Proceedings of the 24th IEEE European Test Symposium, 2019

On-line Testing for Autonomous Systems driven by RISC-V Processor Design Verification.

[BibT_eX]

[DOI]

Annachiara Ruospo

Pasquale Davide Schiavone

Ernesto Sánchez

Angelo Garofalo

Luca Benini

Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

Non-Intrusive Self-Test Library for Automotive Critical Applications: Constraints and Solutions.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018

Test of Reconfigurable Modules in Scan Networks.

[BibT_eX]

[DOI]

Xrysovalantis Kavousianos

IEEE Trans. Computers, 2018

An Evolutionary Algorithm Approach to Stress Program Generation During Burn-In.

[BibT_eX]

[DOI]

J. Low Power Electron., 2018

Adaptive Management Techniques for Optimized Burn-in of Safety-Critical SoC.

[BibT_eX]

[DOI]

J. Electron. Test., 2018

An Optimized Test During Burn-In for Automotive SoC.

[BibT_eX]

[DOI]

IEEE Des. Test, 2018

An analysis of test solutions for COTS-based systems in space applications.

[BibT_eX]

[DOI]

Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

Improved Test Solutions for COTS-Based Systems in Space Applications.

[BibT_eX]

[DOI]

Proceedings of the VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms, 2018

About on-line functionally untestable fault identification in microprocessor cores for safety-critical applications.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE Latin-American Test Symposium, 2018

A New Technique to Generate Test Sequences for Reconfigurable Scan Networks.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2018

A Semi-Formal Technique to Generate Effective Test Sequences for Reconfigurable Scan Networks.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2018

Fault-Independent Test-Generation for Software-Based Self-Testing.

[BibT_eX]

[DOI]

Panagiotis Georgiou

Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

An Evolutionary Technique for Reducing the Duration of Reconfigurable Scan Network Test.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018

2017

New techniques for functional testing of microprocessor based systems.

[BibT_eX]

[DOI]

PhD thesis, 2017

A DMA and CACHE-based stress schema for burn-in of automotive microcontroller.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE Latin American Test Symposium, 2017

On the detection of board delay faults through the execution of functional programs.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE Latin American Test Symposium, 2017

2016

A Flexible Framework for the Automatic Generation of SBST Programs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Development Flow for On-Line Core Self-Test of Automotive Microcontrollers.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

Observability solutions for in-field functional test of processor-based systems: A survey and quantitative test case evaluation.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2016

Effective generation and evaluation of diagnostic SBST programs.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Thermal issues in test: An overview of the significant aspects and industrial practice.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE VLSI Test Symposium, 2016

A suite of IEEE 1687 benchmark networks.

[BibT_eX]

[DOI]

Rene Krenz-Baath

Proceedings of the 2016 IEEE International Test Conference, 2016

Automatic generation of stimuli for fault diagnosis in IEEE 1687 networks.

[BibT_eX]

[DOI]

Erik Larsson

Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

On the diagnostic analysis of IEEE 1687 networks.

[BibT_eX]

[DOI]

Erik Larsson

Proceedings of the 21th IEEE European Test Symposium, 2016

In-field functional test programs development flow for embedded FPUs.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016

Test Time Minimization in Reconfigurable Scan Networks.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015

An evolutionary approach for test program compaction.

[BibT_eX]

[DOI]

Pasquale Davide Schiavone

Marco Gaudesi

Ernesto Sánchez

Giovanni Squillero

Proceedings of the 16th Latin-American Test Symposium, 2015

On the functional test of the cache coherency logic in multi-core systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

On the maximization of the sustained switching activity in a processor.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

Exploiting Evolutionary Computation in an Industrial Flow for the Development of Code-Optimized Microprocessor Test Programs.

[BibT_eX]

[DOI]

Proceedings of the Genetic and Evolutionary Computation Conference, 2015

Software-based self-test techniques of computational modules in dual issue embedded processors.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE European Test Symposium, 2015

On the automatic generation of SBST test programs for in-field test.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

On the testability of IEEE 1687 networks.

[BibT_eX]

[DOI]

Erik Larsson

Proceedings of the 24th IEEE Asian Test Symposium, 2015

2014

On the in-field functional testing of decode units in pipelined RISC processors.

[BibT_eX]

[DOI]

Paolo Bernardi

Lyl M. Ciganda Brasca

Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

2013

On the Functional Test of the Register Forwarding and Pipeline Interlocking Unit in Pipelined Processors.

[BibT_eX]

[DOI]

Paolo Bernardi