Marco Restifo

Orcid: 0000-0003-1729-7237

According to our database1, Marco Restifo authored at least 15 papers between 2017 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2020
Reliability and Testing of Complex Safety-Critical Automotive SoC.
PhD thesis, 2020

Applicative System Level Test introduction to Increase Confidence on Screening Quality.
Proceedings of the 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2020

2019
Innovative Practices on Automotive Test.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019

A Hybrid In-Field Self-Test Technique for SoCs.
Proceedings of the 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2019

Effective Screening of Automotive SoCs by Combining Burn-In and System Level Test.
Proceedings of the 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2019

2018
An Evolutionary Algorithm Approach to Stress Program Generation During Burn-In.
J. Low Power Electron., 2018

Adaptive Management Techniques for Optimized Burn-in of Safety-Critical SoC.
J. Electron. Test., 2018

An Optimized Test During Burn-In for Automotive SoC.
IEEE Des. Test, 2018

About on-line functionally untestable fault identification in microprocessor cores for safety-critical applications.
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018

2017
A DMA and CACHE-based stress schema for burn-in of automotive microcontroller.
Proceedings of the 18th IEEE Latin American Test Symposium, 2017

On the in-field test of embedded memories.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

Scan chain encryption for the test, diagnosis and debug of secure circuits.
Proceedings of the 22nd IEEE European Test Symposium, 2017

On-line software-based self-test for ECC of embedded RAM memories.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

An evolutionary approach to hardware encryption and Trojan-horse mitigation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

A comprehensive methodology for stress procedures evaluation and comparison for Burn-In of automotive SoC.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017


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