Melchiorre Bruccoleri

According to our database, Melchiorre Bruccoleri authored at least 11 papers between 1999 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

Analog Front End of 50-Gb/s SiGe BiCMOS Opto-Electrical Receiver in 3-D-Integrated Silicon Photonics Technology.

Farhad Bozorgi, Melchiorre Bruccoleri, Elham Rahimi, Matteo Repossi, Francesco Svelto, Andrea Mazzanti

IEEE J. Solid State Circuits, 2022

2019

A 26-Gb/s 3-D-Integrated Silicon Photonic Receiver in BiCMOS-55 nm and PIC25G With - 15.2-dBm OMA Sensitivity.

Farhad Bozorgi, Melchiorre Bruccoleri, Matteo Repossi, Enrico Temporiti, Andrea Mazzanti, Francesco Svelto

Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

2016

A High-Swing 45 Gb/s Hybrid Voltage and Current-Mode PAM-4 Transmitter in 28 nm CMOS FDSOI.

Matteo Bassi, Francesco Radice, Melchiorre Bruccoleri, Simone Erba, Andrea Mazzanti

IEEE J. Solid State Circuits, 2016

3.6 A 45Gb/s PAM-4 transmitter delivering 1.3Vppd output swing with 1V supply in 28nm CMOS FDSOI.

Matteo Bassi, Francesco Radice, Melchiorre Bruccoleri, Simone Erba, Andrea Mazzanti

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015

A low-noise programmable-gain amplifier for 25 Gb/s multi-mode fiber receivers in 28nm CMOS FDSOI.

Francesco Radice, Melchiorre Bruccoleri, Enrico Mammei, Matteo Bassi, Andrea Mazzanti

Proceedings of the ESSCIRC Conference 2015, 2015

2014

Analysis and Design of a Power-Scalable Continuous-Time FIR Equalizer for 10 Gb/s to 25 Gb/s Multi-Mode Fiber EDC in 28 nm LP CMOS.

Enrico Mammei, Fabrizio Loi, Francesco Radice, Angelo Dati, Melchiorre Bruccoleri, Matteo Bassi, Andrea Mazzanti

IEEE J. Solid State Circuits, 2014

8.3 A power-scalable 7-tap FIR equalizer with tunable active delay line for 10-to-25Gb/s multi-mode fiber EDC in 28nm LP-CMOS.

Enrico Mammei, Fabrizio Loi, Francesco Radice, Angelo Dati, Melchiorre Bruccoleri, Matteo Bassi, Andrea Mazzanti

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013

A 6-bit 6-GS/s 95mW background calibrated flash ADC with integrating preamplifiers and half-rate comparators in 32nm LP CMOS.

Francesco Radice, Melchiorre Bruccoleri, Marcello Ganzerli, Giorgio Spelgatti, Davide Sanzogni, Massimo Pozzoni, Andrea Mazzanti

Proceedings of the ESSCIRC 2013, 2013

2002

An all-analog CMOS implementation of a turbo decoder for hard-disk drive read channels.

Andrea Xotta, Daniele Vogrig, Andrea Gerosa, Andrea Neviani, Alexandre Graell i Amat, Guido Montorsi, Melchiorre Bruccoleri, Giorgio Betti

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2000

A 450 Mbit/s parallel read/write channel with parity check and 16-state time variant Viterbi.

Giacomino Bollati, Angelo Dati, Giorgio Betti, Ivan Bietti, Francesco Brianti, Melchiorre Bruccoleri, M. Coltella, P. Demartini, Marco Demicheli, Paolo Gadducci, Stefano Marchese, Daniele Ottini, Valerio Pisati, Francesco Rezzi, A. Rossi, P. Savo, C. Tonci, Rinaldo Castello

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

1999

A 450 Mbit/s EPR4 PRML read/write channel.

Marco Demicheli, Giacomino Bollati, Paolo Gadducci, L. Affortunati, Roberto Alini, G. Betti, I. Bietti, F. Brianti, Melchiorre Bruccoleri, M. Coltella, P. Demartini, Stefano Marchese, D. Ottini, Valerio Pisati, Salvatore Portaluri, A. Rossi, P. Savo, C. Tonci, Rinaldo Castello

Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999