Igor Loi

According to our database1, Igor Loi authored at least 56 papers between 2007 and 2022.

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Bibliography

2022
Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode.
IEEE J. Solid State Circuits, 2022

2021
Vega: A 10-Core SoC for IoT End-Nodes with DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode.
CoRR, 2021

4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2020
Energy-Efficient Two-level Instruction Cache Design for an Ultra-Low-Power Multi-core Cluster.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Mr.Wolf: An Energy-Precision Scalable Parallel Ultra Low Power SoC for IoT Edge Processing.
IEEE J. Solid State Circuits, 2019

2018
Neurostream: Scalable and Energy Efficient Deep Learning with Smart Memory Cubes.
IEEE Trans. Parallel Distributed Syst., 2018

The Quest for Energy-Efficient I$ Design in Ultra-Low-Power Clustered Many-Cores.
IEEE Trans. Multi Scale Comput. Syst., 2018

A Heterogeneous Multicore System on Chip for Energy Efficient Brain Inspired Computing.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

Sub-mW multi-Gbps chip-to-chip communication Links for Ultra-Low Power IoT end-nodes.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Mr. Wolf: A 1 GFLOP/s Energy-Proportional Parallel Ultra Low Power SoC for IOT Edge Processing.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

GAP-8: A RISC-V SoC for AI at the Edge of the IoT.
Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018

2017
Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Logic-Base Interconnect Design for Near Memory Computing in the Smart Memory Cube.
IEEE Trans. Very Large Scale Integr. Syst., 2017

An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster.
IEEE Micro, 2017

A Hybrid Instruction Prefetching Mechanism for Ultra Low-Power Multicore Clusters.
IEEE Embed. Syst. Lett., 2017

A Self-Aware Architecture for PVT Compensation and Power Nap in Near Threshold Processors.
IEEE Des. Test, 2017

2016
PULP: A Ultra-Low Power Parallel Accelerator for Energy-Efficient and Flexible Embedded Vision.
J. Signal Process. Syst., 2016

On-the-fly adaptivity for process networks over shared-memory platforms.
Microprocess. Microsystems, 2016

A high-efficiency runtime reconfigurable IP for CNN acceleration on a mid-range all-programmable SoC.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

A heterogeneous multi-core system-on-chip for energy efficient brain inspired vision.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing.
Proceedings of the 2016 IEEE Symposium in Low-Power and High-Speed Chips, 2016

Curbing the roofline: a scalable and flexible architecture for CNNs on FPGA.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

Design and Evaluation of a Processing-in-Memory Architecture for the Smart Memory Cube.
Proceedings of the Architecture of Computing Systems - ARCS 2016, 2016

2015
A Modular Shared L2 Memory Design for 3-D Integration.
IEEE Trans. Very Large Scale Integr. Syst., 2015

PULP: A parallel ultra low power platform for next generation IoT applications.
Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015

High performance AXI-4.0 based interconnect for extensible smart memory cubes.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Exploring multi-banked shared-L1 program cache on ultra-low power, tightly coupled processor clusters.
Proceedings of the 12th ACM International Conference on Computing Frontiers, 2015

2014
Energy-efficient vision on the PULP platform for ultra-low power parallel computing.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014

Online process transformation for polyhedral process networks in shared-memory MPSoCs.
Proceedings of the 3rd Mediterranean Conference on Embedded Computing, 2014

A Stream Buffer Mechanism for Pervasive Splitting Transformations on Polyhedral Process Networks.
Proceedings of the 2nd International Workshop on Many-core Embedded Systems, 2014

A multi banked - Multi ported - Non blocking shared L2 cache for MPSoC platforms.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Ultra-low-latency lightweight DMA for tightly coupled multi-core clusters.
Proceedings of the Computing Frontiers Conference, CF'14, 2014

2013
Exploration and Optimization of 3-D Integrated DRAM Subsystems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

A case for three-dimensional stacking of tightly coupled data memories over multi-core clusters using low-latency interconnects.
IET Comput. Digit. Tech., 2013

3D logarithmic interconnect: Stacking multiple L1 memory dies over multi-core clusters.
Proceedings of the 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2013

A shared-FPU architecture for ultra-low power MPSoCs.
Proceedings of the Computing Frontiers Conference, 2013

A high-performance multiported L2 memory IP for scalable three-dimensional integration.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2012
Variation-Tolerant Architecture for Ultra Low Power Shared-L1 Processor Clusters.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

Configurable Low-Latency Interconnect for Multi-core Clusters.
Proceedings of the VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design, 2012

3D-LIN: A configurable low-latency interconnect for multi-core clusters with 3D stacked L1 memory.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

An energy efficient DRAM subsystem for 3D integrated SoCs.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

A resilient architecture for low latency communication in shared-L1 processor clusters.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Design Issues and Considerations for Low-Cost 3-D TSV IC Technology.
IEEE J. Solid State Circuits, 2011

Power/Performance Exploration of Single-core and Multi-core Processor Approaches for Biomedical Signal Processing.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

Design space exploration for 3D-stacked DRAMs.
Proceedings of the Design, Automation and Test in Europe, 2011

A fully-synthesizable single-cycle interconnection network for Shared-L1 processor clusters.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
3D NoCs - Unifying inter & intra chip communication.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A new physical routing approach for robust bundled signaling on NoC links.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

An efficient distributed memory interface for many-core platform with 3D stacked DRAM.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Synthesis of low-overhead configurable source routing tables for network interfaces.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
A low-overhead fault tolerance scheme for TSV-based 3D network on chip links.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Developing Mesochronous Synchronizers to Enable 3D NoCs.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Area and Power Modeling for Networks-on-Chip with Layout Awareness.
VLSI Design, 2007

Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow.
Proceedings of the 2nd Internationa ICST Conference on Nano-Networks, 2007


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