Riccardo Cattaneo

According to our database1, Riccardo Cattaneo authored at least 21 papers between 2012 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Bibliography

2016
On How to Accelerate Iterative Stencil Loops: A Scalable Streaming-Based Approach.
TACO, 2016

A polyhedral model-based framework for dataflow implementation on FPGA devices of iterative stencil loops.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

2015
On how to efficiently accelerate brain network analysis on FPGA-based computing system.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

A multiobjective reconfiguration-aware scheduler for FPGA-based heterogeneous architectures.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Explicitly isolating data and computation in high level synthesis: the role of polyhedral framework.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Relocation-Aware Floorplanning for Partially-Reconfigurable FPGA-Based Systems.
Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium Workshop, 2015

K-Ways Partitioning of Polyhedral Process Networks: A Multi-level Approach.
Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium Workshop, 2015

Thermal-aware floorplanning for partially-reconfigurable FPGA-based systems.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Power-awareness and smart-resource management in embedded computing systems.
Proceedings of the 2015 International Conference on Hardware/Software Codesign and System Synthesis, 2015

2014
FPGA-Based Design Using the FASTER Toolchain: The Case of STM Spear Development Board.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014

Adaptive Raytracing Implementation Using Partial Dynamic Reconfiguration.
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

PaRA-Sched: A Reconfiguration-Aware Scheduler for Reconfigurable Architectures.
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

2013
SMASH: A heuristic methodology for designing partially reconfigurable MPSoCs.
Proceedings of the 24th IEEE International Symposium on Rapid System Prototyping, 2013

A framework for effective exploitation of partial reconfiguration in dataflow computing.
Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013

A Flexible Interconnection Structure for Reconfigurable FPGA Dataflow Applications.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

The autonomic operating system research project: achievements and future directions.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

A2B: An integrated framework for designing heterogeneous and reconfigurable systems.
Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013

Runtime adaptation on dataflow HPC platforms.
Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013

ThermOS: System support for dynamic thermal management of chip multi-processors.
Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, 2013

2012
A Framework for Thermal and Performance Management.
Proceedings of the 2012 Workshop on Managing Systems Automatically and Dynamically, 2012

An Enhanced Relocation Manager to Speedup Core Allocation in FPGA-based Reconfigurable Systems.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012


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