Catalin Bogdan Ciobanu
According to our database1, Catalin Bogdan Ciobanu authored at least 22 papers between 2009 and 2018.
Legend:Book In proceedings Article PhD thesis Other
The Case for Polymorphic Registers in Dataflow Computing.
International Journal of Parallel Programming, 2018
EXTRA: an open platform for reconfigurable architectures.
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018
MAX-PolyMem: High-Bandwidth Polymorphic Parallel Memories for DFEs.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018
Towards Application-Centric Parallel Memories.
Proceedings of the Euro-Par 2018: Parallel Processing Workshops, 2018
A CAD Open Platform for High Performance Reconfigurable Systems in the EXTRA Project.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
A NoC-based custom FPGA configuration memory architecture for ultra-fast micro-reconfiguration.
Proceedings of the International Conference on Field Programmable Technology, 2017
An open reconfigurable research platform as stepping stone to exascale high-performance computing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
EXTRA: Towards the exploitation of eXascale technology for reconfigurable architectures.
Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2016
FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration.
Microprocessors and Microsystems - Embedded Hardware Design, 2015
EXTRA: Towards an Efficient Open Platform for Reconfigurable High Performance Computing.
Proceedings of the 18th IEEE International Conference on Computational Science and Engineering, 2015
Real-Time Olivary Neuron Simulations on Dataflow Computing Machines.
Proceedings of the Supercomputing - 29th International Conference, 2014
Customizable Register Files for Multidimensional SIMD Architectures.
PhD thesis, 2013
Dataflow computing with Polymorphic Registers.
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013
FASTER run-time reconfiguration management.
Proceedings of the International Conference on Supercomputing, 2013
Separable 2D Convolution with Polymorphic Register Files.
Proceedings of the Architecture of Computing Systems - ARCS 2013, 2013
On implementability of Polymorphic Register Files.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012
Scalability Study of Polymorphic Register Files.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
Novel Design Methods and a Tool Flow for Unleashing Dynamic Reconfiguration.
Proceedings of the 15th IEEE International Conference on Computational Science and Engineering, 2012
Scalability Evaluation of a Polymorphic Register File: A CG Case Study.
Proceedings of the Architecture of Computing Systems - ARCS 2011, 2011
The SARC Architecture.
IEEE Micro, 2010
A Polymorphic Register File for matrix operations.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010
Wave field synthesis for 3D audio: architectural prospectives.
Proceedings of the 6th Conference on Computing Frontiers, 2009