Yusuke Kanno

According to our database, Yusuke Kanno authored at least 9 papers between 2006 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2020

Design Method for Online Totally Self-Checking Comparators Implementable on FPGAs.

Yusuke Kanno, Tadanobu Toba, Kotaro Shimamura, Nobuyasu Kanekawa

IEEE Trans. Very Large Scale Integr. Syst., 2020

2017

Soft-Error-Tolerant Dual-Modular-Redundancy Architecture with Repair and Retry Scheme for Memory-Control Circuit on FPGA.

Makoto Saen, Tadanobu Toba, Yusuke Kanno

IEICE Trans. Electron., 2017

2014

A Method for Measuring of RTN by Boosting Word-Line Voltage in 6-Tr-SRAMs.

Goichi Ono, Yuki Mori, Michiaki Nakayama, Yusuke Kanno

IEICE Trans. Electron., 2014

2012

Comprehensive electrochemical imaging with local redox cycling-based electrochemical chip device for evaluation of three-dimensional culture cells.

Kosuke Ino, Mustafa Sen, Taku Nishijo, Yusuke Kanno, Hitoshi Shiku, Tomokazu Matsue

Proceedings of the International Symposium on Micro-NanoMechatronics and Human Science, 2012

2010

A Low-Power Wide-Range Clock Synchronizer With Predictive-Delay-Adjustment Scheme for Continuous Voltage Scaling in DVFS.

Masafumi Onouchi, Yusuke Kanno, Makoto Saen, Shigenobu Komatsu, Yoshihiko Yasu, Koichiro Ishibashi

IEEE J. Solid State Circuits, 2010

2007

Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs.

Yusuke Kanno, Hiroyuki Mizuno, Yoshihiko Yasu, Kenji Hirose, Yasuhisa Shimazaki, Tadashi Hoshi, Yujiro Miyairi, Toshifumi Ishii, Tetsuya Yamada, Takahiro Irita, Toshihiro Hattori, Kazumasa Yanagisawa, Naohiko Irie

IEEE J. Solid State Circuits, 2007

In-Situ Measurement of Supply-Noise Maps With Millivolt Accuracy and Nanosecond-Order Time Resolution.

Yusuke Kanno, Yuki Kondoh, Takahiro Irita, Kenji Hirose, Ryo Mori, Yoshihiko Yasu, Shigenobu Komatsu, Hiroyuki Mizuno

IEEE J. Solid State Circuits, 2007

2006

Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor.

Yusuke Kanno, Hiroyuki Mizuno, Yoshihiko Yasu, Kenji Hirose, Yasuhisa Shimazaki, Tadashi Hoshi, Yujiro Miyairi, Toshifumi Ishii, Tetsuya Yamada, Takahiro Irita, Toshihiro Hattori, Kazumasa Yanagisawa, Naohiko Irie

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

Hierarchical power distribution and power management scheme for a single chip mobile processor.

Toshihiro Hattori, Takahiro Irita, Masayuki Ito, Eiji Yamamoto, Hisashi Kato, Go Sado, Tetsuhiro Yamada, Kunihiko Nishiyama, Hiroshi Yagi, Takao Koike, Yoshihiko Tsuchihashi, Motoki Higashida, Hiroyuki Asano, Izumi Hayashibara, Ken Tatezawa, Yasuhisa Shimazaki, Naozumi Morino, Yoshihiko Yasu, Tadashi Hoshi, Yujiro Miyairi, Kazumasa Yanagisawa, Kenji Hirose, Saneaki Tamaki, Shinichi Yoshioka, Toshifumi Ishii, Yusuke Kanno, Hiroyuki Mizuno, Tetsuya Yamada, Naohiko Irie, Reiko Tsuchihashi, Nobuto Arai, Tomohiro Akiyama, Koji Ohno

Proceedings of the 43rd Design Automation Conference, 2006