Guido Bertoni
Orcid: 0000-0002-5122-1589
According to our database1,
Guido Bertoni
authored at least 67 papers
between 2001 and 2025.
Collaborative distances:
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Bibliography
2025
Unveiling ECC Vulnerabilities: LSTM Networks for Operation Recognition in Side-Channel Attacks.
CoRR, February, 2025
Design, Implementation and Validation of NSCP: A New Secure Channel Protocol for Hardened IoT.
Proceedings of the Design, Automation & Test in Europe Conference, 2025
2023
2018
CASCA: A Design Automation Approach for Designing Hardware Countermeasures Against Side-Channel Attacks.
ACM Trans. Design Autom. Electr. Syst., 2018
IEEE Trans. Computers, 2018
IACR Cryptol. ePrint Arch., 2018
Proceedings of the 2018 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2018
Proceedings of the Topics in Cryptology - CT-RSA 2018, 2018
Proceedings of the Applied Cryptography and Network Security, 2018
2017
IACR Trans. Symmetric Cryptol., 2017
J. Hardw. Syst. Secur., 2017
2016
ACM J. Emerg. Technol. Comput. Syst., 2016
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2016
Proceedings of the 2nd International Conference on Information Systems Security and Privacy, 2016
2015
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2015
2014
Proceedings of the Applied Cryptography and Network Security, 2014
2013
A fault induction technique based on voltage underfeeding with application to attacks against AES and RSA.
J. Syst. Softw., 2013
2012
Proceedings of the Fault Analysis in Cryptography, 2012
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012
2011
Fault attack to the elliptic curve digital signature algorithm with multiple bit faults.
Proceedings of the 4th International Conference on Security of Information and Networks, 2011
Proceedings of the Selected Areas in Cryptography - 18th International Workshop, 2011
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011
2010
IACR Cryptol. ePrint Arch., 2010
Proceedings of the Cryptographic Hardware and Embedded Systems, 2010
Proceedings of the Sixth International Conference on Information Assurance and Security, 2010
Proceedings of the Secure Integrated Circuits and Systems, 2010
2009
IACR Cryptol. ePrint Arch., 2009
Proceedings of the Sixth International Conference on Information Technology: New Generations, 2009
Proceedings of the Sixth International Workshop on Fault Diagnosis and Tolerance in Cryptography, 2009
Proceedings of the Symmetric Cryptography, 11.01. - 16.01.2009, 2009
Proceedings of the Symmetric Cryptography, 11.01. - 16.01.2009, 2009
2008
IEEE Trans. Computers, 2008
A 640 Mbit/S 32-Bit Pipelined Implementation of the AES Algorithm.
Proceedings of the SECRYPT 2008, 2008
Proceedings of the Fifth International Conference on Information Technology: New Generations (ITNG 2008), 2008
Proceedings of the Advances in Cryptology, 2008
2006
Proceedings of the 4th IEEE Conference on Pervasive Computing and Communications Workshops (PerCom 2006 Workshops), 2006
Proceedings of the Third International Conference on Information Technology: New Generations (ITNG 2006), 2006
Proceedings of the Third International Conference on Information Technology: New Generations (ITNG 2006), 2006
Proceedings of the Computational Science and Its Applications, 2006
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006
2005
Proceedings of the International Symposium on Information Technology: Coding and Computing (ITCC 2005), 2005
Proceedings of the International Symposium on Information Technology: Coding and Computing (ITCC 2005), 2005
2004
Efficient and reliable algorithms and architectures for innovative complex cryptographic systems.
PhD thesis, 2004
Finding Optimum Parallel Coprocessor Design for Genus 2 Hyperelliptic Curve Cryptosystems.
Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04), 2004
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004
2003
Error Analysis and Detection Procedures for a Hardware Implementation of the Advanced Encryption Standard.
IEEE Trans. Computers, 2003
About the performances of the Advanced Encryption Standard in embedded systems with cache memory.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Systolic and Scalable Architectures for Digit-Serial Multiplication in Fields GF(p<sup>m</sup>).
Proceedings of the Progress in Cryptology, 2003
Detecting and Locating Faults in VLSI Implementations of the Advanced Encryption Standard.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003
Proceedings of the Topics in Cryptology, 2003
Concurrent Fault Detection in a Hardware Implementation of the RC5 Encryption Algorithm.
Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003
2002
A Parity Code Based Fault Detection for an Implementation of the Advanced Encryption Standard.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002
Proceedings of the Cryptographic Hardware and Embedded Systems, 2002
On the Propagation of Faults and Their Detection in a Hardware Implementation of the Advanced Encryption Standard.
Proceedings of the 13th IEEE International Conference on Application-Specific Systems, 2002
2001
Efficient finite field digital-serial multiplier architecture for cryptography applications.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001