Gianluca Palermo
Orcid: 0000-0001-7955-8012Affiliations:
- Polytechnic University of Milan, Department of Electronics, Italy
According to our database1,
Gianluca Palermo
authored at least 180 papers
between 2003 and 2024.
Collaborative distances:
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Bibliography
2024
GPU-optimized approaches to molecular docking-based virtual screening in drug discovery: A comparative analysis.
J. Parallel Distributed Comput., April, 2024
Integrating Bayesian Optimization and Machine Learning for the Optimal Configuration of Cloud Systems.
IEEE Trans. Cloud Comput., 2024
A System Development Kit for Big Data Applications on FPGA-based Clusters: The EVEREST Approach.
CoRR, 2024
Proceedings of the 32nd Euromicro International Conference on Parallel, 2024
Unlocking performance portability on LUMI-G supercomputer: A virtual screening case study.
Proceedings of the 12th International Workshop on OpenCL and SYCL, 2024
2023
EXSCALATE: An Extreme-Scale Virtual Screening Platform for Drug Discovery Targeting Polypharmacology to Fight SARS-CoV-2.
IEEE Trans. Emerg. Top. Comput., 2023
Using Artificial Neural Networks to Couple Satellite C-Band Synthetic Aperture Radar Interferometry and Alpine3D Numerical Model for the Estimation of Snow Cover Extent, Height, and Density.
IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 2023
Improving computation efficiency using input and architecture features for a virtual screening application.
CoRR, 2023
Domain-Specific Energy Modeling for Drug Discovery and Magnetohydrodynamics Applications.
Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, 2023
Proceedings of the Euro-Par 2023: Parallel Processing - 29th International Conference on Parallel and Distributed Computing, Limassol, Cyprus, August 28, 2023
Proceedings of the 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2023
Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023
Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023
Tunable and Portable Extreme-Scale Drug Discovery Platform at Exascale: the LIGATE Approach.
Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023
2022
IEEE Trans. Software Eng., 2022
J. Supercomput., 2022
GPU-optimized Approaches to Molecular Docking-based Virtual Screening in Drug Discovery: A Comparative Analysis.
CoRR, 2022
CoRR, 2022
Proceedings of the IWOCL'22: International Workshop on OpenCL, Bristol, United Kingdom, May 10, 2022
Snow-Mantle Remote Sensing from Spaceborne Sar Interferometry Using a Model-Based Synergetic Retrieval Approach in Central Apennines.
Proceedings of the IEEE International Geoscience and Remote Sensing Symposium, 2022
Proceedings of the CF '22: 19th ACM International Conference on Computing Frontiers, Turin, Italy, May 17, 2022
2021
Tunable approximations to control time-to-solution in an HPC molecular docking Mini-App.
J. Supercomput., 2021
An Efficient Monte Carlo-Based Probabilistic Time-Dependent Routing Calculation Targeting a Server-Side Car Navigation System.
IEEE Trans. Emerg. Top. Comput., 2021
CoRR, 2021
EXSCALATE: An extreme-scale in-silico virtual screening platform to evaluate 1 trillion compounds in 60 hours on 81 PFLOPS supercomputers.
CoRR, 2021
Dynamic Network Selection for the Object Detection Task: Why It Matters and What We (Didn't) Achieve.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2021
Understanding the I/O Impact on the Performance of High-Throughput Molecular Docking.
Proceedings of the 6th IEEE/ACM International Parallel Data Systems Workshop, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
EVEREST: A design environment for extreme-scale big data analytics on heterogeneous platforms.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
SN Comput. Sci., 2020
A Collaborative Filtering Approach for the Automatic Tuning of Compiler Optimisations.
Proceedings of the 21st ACM SIGPLAN/SIGBED International Conference on Languages, 2020
2019
Exploiting OpenMP and OpenACC to accelerate a geometric approach to molecular docking in heterogeneous HPC nodes.
J. Supercomput., 2019
IEEE Trans. Computers, 2019
Microprocess. Microsystems, 2019
Workload- and process-variation aware voltage/frequency tuning for energy efficient performance sustainability of NTC manycores.
Integr., 2019
Exploiting OpenMP & OpenACC to Accelerate a Molecular Docking Mini-App in Heterogeneous HPC Nodes.
CoRR, 2019
Supporting the Scale-Up of High Performance Application to Pre-Exascale Systems: The ANTAREX Approach.
Proceedings of the 27th Euromicro International Conference on Parallel, 2019
An hybrid approach to accelerate a molecular docking application for virtual screening in heterogeneous nodes: POSTER.
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019
2018
Int. J. Parallel Program., 2018
Design Space Pruning and Computational Workload Splitting for Autotuning OpenCL Applications.
Proceedings of the RAPIDO 2018 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2018
Proceedings of the 6th International Workshop on Parallelism in Bioinformatics, 2018
ANTAREX: A DSL-Based Approach to Adaptively Optimizing and Enforcing Extra-Functional Properties in High Performance Computing.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018
SOCRATES - A seamless online compiler and system runtime autotuning framework for energy-aware applications.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018
SpringerBriefs in Applied Sciences and Technology, Springer, ISBN: 978-3-319-71489-9, 2018
2017
Exploring Efficient Hardware Support for Applications with Irregular Memory Patterns on Multinode Manycore Architectures.
IEEE Trans. Parallel Distributed Syst., 2017
MiCOMP: Mitigating the Compiler Phase-Ordering Problem Using Optimization Sub-Sequences and Machine Learning.
ACM Trans. Archit. Code Optim., 2017
CONTREX: Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties.
Microprocess. Microsystems, 2017
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017
Early Stage Interference Checking for Automatic Design Space Exploration of Mixed Critical Systems.
Proceedings of the 9th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2017
2016
ACM Trans. Archit. Code Optim., 2016
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016
A System-Level Exploration of Power Delivery Architectures for Near-Threshold Manycores Considering Performance Constraints.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Proceedings of the 7th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and the 5th Workshop on Design Tools and Architectures For Multicore Embedded Computing Platforms, 2016
CONTREX: Design of Embedded Mixed-Criticality CONTRol Systems under Consideration of EXtra-Functional Properties.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016
Autotuning and adaptivity approach for energy efficient Exascale HPC systems: The ANTAREX approach.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the 1st International Workshop on RESource Awareness and Application Auto-tuning in Adaptive and heterogeNeous compuTing co-located with 19th International Conference on Design, 2016
Proceedings of the 1st International Workshop on RESource Awareness and Application Auto-tuning in Adaptive and heterogeNeous compuTing co-located with 19th International Conference on Design, 2016
Proceedings of the 1st International Workshop on RESource Awareness and Application Auto-tuning in Adaptive and heterogeNeous compuTing co-located with 19th International Conference on Design, 2016
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016
Variability-Aware Voltage Island Management for Near-Threshold Computing with Performance Guarantees.
Proceedings of the Near Threshold Computing, Technology, Methods and Applications., 2016
2015
Virtual Platform-Based Design Space Exploration of Power-Efficient Distributed Embedded Applications.
ACM Trans. Embed. Comput. Syst., 2015
SPIRIT: Spectral-Aware Pareto Iterative Refinement Optimization for Supervised High-Level Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
DeSpErate++: An Enhanced Design Space Exploration Framework Using Predictive Simulation Scheduling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015
An efficient joint analytical and simulation-based design space exploration flow for predictable multi-core systems.
Proceedings of the 2015 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2015
Customization of OpenCL applications for efficient task mapping under heterogeneous platform constraints.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
ANTAREX - AutoTuning and Adaptivity appRoach for Energy Efficient eXascale HPC Systems.
Proceedings of the 18th IEEE International Conference on Computational Science and Engineering, 2015
Proceedings of the AMIA 2015, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
The COMPLEX methodology for UML/MARTE Modeling and design space exploration of embedded systems.
J. Syst. Archit., 2014
Combining application adaptivity and system-wide Resource Management on multi-core platforms.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014
OpenCL Application Auto-tuning and Run-Time Resource Management for Multi-core Platforms.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014
Proceedings of the 12th IEEE Symposium on Embedded Systems for Real-time Multimedia, 2014
Voltage island management in near threshold manycore architectures to mitigate dark silicon.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
DeSpErate: Speeding-up design space exploration by using predictive simulation scheduling.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Variation-aware voltage island formation for power efficient near-threshold manycore architectures.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014
Evaluating orthogonality between application auto-tuning and run-time resource management for adaptive OpenCL applications.
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014
Data Parallel Application Adaptivity and System-Wide Resource Management in Many-Core Architectures.
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014
2013
ACM Trans. Embed. Comput. Syst., 2013
ARTE: An Application-specific Run-Time managEment framework for multi-cores based on queuing models.
Parallel Comput., 2013
The COMPLEX reference framework for HW/SW co-design and power management supporting platform-based design-space exploration.
Microprocess. Microsystems, 2013
A framework for Compiler Level statistical analysis over customized VLIW architecture.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013
Exploring manycore multinode systems for irregular applications with FPGA prototyping.
Proceedings of the 2013 IEEE Hot Chips 25 Symposium (HCS), 2013
Run-time optimization of a dynamically reconfigurable embedded system through performance prediction.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013
A meta-model assisted coprocessor synthesis framework for compiler/architecture parameters customization.
Proceedings of the Design, Automation and Test in Europe, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
Exploring hardware support for scaling irregular applications on multi-node multi-core architectures.
Proceedings of the 24th International Conference on Application-Specific Systems, 2013
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2013
2012
A Variability-Aware Robust Design Space Exploration Methodology for On-Chip Multiprocessors Subject to Application-Specific Constraints.
ACM Trans. Embed. Comput. Syst., 2012
OSCAR: An Optimization Methodology Exploiting Spatial Correlation in Multicore Design Spaces.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Parallel paradigms and run-time management techniques for many-core architectures: the 2PARMA approach.
Proceedings of the 2012 Interconnection Network Architecture, 2012
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
Using multi-objective design space exploration to enable run-time resource management for reconfigurable architectures.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012
An exploration methodology for a customizable OpenCL stereo-matching application targeted to an industrial multi-cluster architecture.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012
Evaluating Run-time Resource Management Policies for Multi-core Embedded Platforms with the EMME Evaluation Framework.
Proceedings of the ARCS 2012 Workshops, 28. Februar - 2. März 2012, München, Germany, 2012
2011
Linking run-time resource management of embedded multi-core platforms with automated design-time exploration.
IET Comput. Digit. Tech., 2011
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
Proceedings of the IEEE 9th Symposium on Application Specific Processors, 2011
Invited paper: Parallel programming and run-time resource management framework for many-core platforms: The 2PARMA approach.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011
Floorplanning-aware design space exploration for application-specific hierarchical networks on-chip.
Proceedings of the 4th International Workshop on Network on Chip Architectures, 2011
Proceedings of the Architecture of Computing Systems - ARCS 2011, 2011
Proceedings of the Multi-objective Design Space Exploration of Multiprocessor SoC Architectures, 2011
Proceedings of the Multi-objective Design Space Exploration of Multiprocessor SoC Architectures, 2011
Proceedings of the Multi-objective Design Space Exploration of Multiprocessor SoC Architectures, 2011
Design Space Exploration for Run-Time Management of a Reconfigurable System for Video Streaming.
Proceedings of the Multi-objective Design Space Exploration of Multiprocessor SoC Architectures, 2011
Proceedings of the Multi-objective Design Space Exploration of Multiprocessor SoC Architectures, 2011
Proceedings of the Multi-objective Design Space Exploration of Multiprocessor SoC Architectures, 2011
2010
Proceedings of the Third International Workshop on Network on Chip Architectures, 2010
Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010
2PARMA: Parallel Paradigms and Run-Time Management Techniques for Many-Core Architectures.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-Core Architectures.
Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010
A reconfigurable multiprocessor architecture for a reliable face recognition implementation.
Proceedings of the Design, Automation and Test in Europe, 2010
An industrial design space exploration framework for supporting run-time resource management on multi-core systems.
Proceedings of the Design, Automation and Test in Europe, 2010
Energy-performance design space exploration in SMT architectures exploiting selective load value predictions.
Proceedings of the Design, Automation and Test in Europe, 2010
A correlation-based design space exploration methodology for multi-processor systems-on-chip.
Proceedings of the 47th Design Automation Conference, 2010
Multicube Explorer: An Open Source Framework for Design Space Exploration of Chip Multi-Processors.
Proceedings of the ARCS '10, 2010
2009
ReSPIR: A Response Surface-Based Pareto Iterative Refinement for Application-Specific Design Space Exploration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
A design space exploration methodology supporting run-time resource management for multi-processor Systems-on-chip.
Proceedings of the IEEE 7th Symposium on Application Specific Processors, 2009
Multi-processor system-on-chip Design Space Exploration based on multi-level modeling techniques.
Proceedings of the 2009 International Conference on Embedded Computer Systems: Architectures, 2009
Proceedings of the Second International Workshop on Network on Chip Architectures, 2009
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009
Meta-model Assisted Optimization for Design Space Exploration of Multi-Processor Systems-on-Chip.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
Prototyping pipelined applications on a heterogeneous FPGA multiprocessor virtual platform.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
Variability-aware robust design space exploration of chip multiprocessor architectures.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
J. Syst. Archit., 2008
An Efficient Design Space Exploration Methodology for On-Chip Multiprocessors Subject to Application-Specific Constraints.
Proceedings of the IEEE Symposium on Application Specific Processors, 2008
An efficient design space exploration methodology for multiprocessor SoC architectures based on response surface methods.
Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, 2008
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008
Proceedings of the 6th IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, 2008
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008
Proceedings of the Design, Automation and Test in Europe, 2008
Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008
Efficiency and scalability of barrier synchronization on NoC based many-core architectures.
Proceedings of the 2008 International Conference on Compilers, 2008
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008
2007
Exploration of distributed shared memory architectures for NoC-based multiprocessors.
J. Syst. Archit., 2007
Des. Autom. Embed. Syst., 2007
Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007
Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007
Proceedings of the 2nd Internationa ICST Conference on Nano-Networks, 2007
An Internal Partial Dynamic Reconfiguration Implementation of the JPEG Encoder for Low-Cost FPGAsb.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
Proceedings of the Embedded System Design: Topics, Techniques and Trends, IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), May 30, 2007
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007
Proceedings of the IEEE Congress on Evolutionary Computation, 2007
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007
Mapping and Topology Customization Approaches for Application-Specific STNoC Designs.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007
2006
PhD thesis, 2006
IEEE Trans. Very Large Scale Integr. Syst., 2006
SIGARCH Comput. Archit. News, 2006
Power/performance hardware optimization for synchronization intensive applications in MPSoCs.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Using speculative computation and parallelizing techniques to improve scheduling of control based designs.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
2005
J. Embed. Comput., 2005
Low-power branch prediction techniques for VLIW architectures: a compiler-hints based approach.
Integr., 2005
Proceedings of the International Symposium on Information Technology: Coding and Computing (ITCC 2005), 2005
Proceedings of the Euro-Par 2005, Parallel Processing, 11th International Euro-Par Conference, Lisbon, Portugal, August 30, 2005
Fast Dynamic Memory Integration in Co-Simulation Frameworks for Multiprocessor System on-Chip.
Proceedings of the 2005 Design, 2005
Energy/Performance Evaluation of the Multithreaded Extension of a Multicluster VLIW Processor.
Proceedings of the Seventh International Workshop on Computer Architectures for Machine Perception (CAMP 2005), 2005
2004
Multi-objective co-exploration of source code transformations and design space architectures for low-power embedded systems.
Proceedings of the 2004 ACM Symposium on Applied Computing (SAC), 2004
PIRATE: A Framework for Power/Performance Exploration of Network-on-Chip Architectures.
Proceedings of the Integrated Circuit and System Design, 2004
Power-aware branch prediction techniques: a compiler-hints based approach for VLIW processors.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004
Plug-in of power models in the StepNP exploration platform: analysis of power/performance trade-offs.
Proceedings of the 2004 International Conference on Compilers, 2004
2003
A Flexible Framework for Fast Multi-objective Design Space Exploration of Embedded Systems.
Proceedings of the Integrated Circuit and System Design, 2003
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003
Power-Performance System-Level Exploration of a MicroSPARC2-Based Embedded Architecture.
Proceedings of the 2003 Design, 2003