Vittorio Zaccaria
Orcid: 0000-0001-5685-9795Affiliations:
- Polytechnic University of Milan, Italy
According to our database1,
Vittorio Zaccaria
authored at least 90 papers
between 2000 and 2023.
Collaborative distances:
Collaborative distances:
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Bibliography
2023
Interruptible Remote Attestation of Low-end IoT Microcontrollers via Performance Counters.
ACM Trans. Embed. Comput. Syst., September, 2023
IACR Cryptol. ePrint Arch., 2023
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2023
2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2020
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2020
IACR Cryptol. ePrint Arch., 2020
2019
Proceedings of the Web Engineering - 19th International Conference, 2019
2018
CASCA: A Design Automation Approach for Designing Hardware Countermeasures Against Side-Channel Attacks.
ACM Trans. Design Autom. Electr. Syst., 2018
IEEE Trans. Computers, 2018
Toward truly personal chatbots: on the development of custom conversational assistants.
Proceedings of the 1st International Workshop on Software Engineering for Cognitive Services, 2018
Proceedings of the 2018 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2018
Proceedings of the Advanced Information Systems Engineering, 2018
2017
IEEE Trans. Computers, 2017
2016
Proceedings of the Rapid Mashup Development Tools, 2016
2015
SPIRIT: Spectral-Aware Pareto Iterative Refinement Optimization for Supervised High-Level Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
DeSpErate++: An Enhanced Design Space Exploration Framework Using Predictive Simulation Scheduling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
Customization of OpenCL applications for efficient task mapping under heterogeneous platform constraints.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
Combining application adaptivity and system-wide Resource Management on multi-core platforms.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014
OpenCL Application Auto-tuning and Run-Time Resource Management for Multi-core Platforms.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014
DeSpErate: Speeding-up design space exploration by using predictive simulation scheduling.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Evaluating orthogonality between application auto-tuning and run-time resource management for adaptive OpenCL applications.
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014
Data Parallel Application Adaptivity and System-Wide Resource Management in Many-Core Architectures.
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014
2013
ACM Trans. Embed. Comput. Syst., 2013
ARTE: An Application-specific Run-Time managEment framework for multi-cores based on queuing models.
Parallel Comput., 2013
A framework for Compiler Level statistical analysis over customized VLIW architecture.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013
Run-time optimization of a dynamically reconfigurable embedded system through performance prediction.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013
A meta-model assisted coprocessor synthesis framework for compiler/architecture parameters customization.
Proceedings of the Design, Automation and Test in Europe, 2013
Improving simulation speed and accuracy for many-core embedded platforms with ensemble models.
Proceedings of the Design, Automation and Test in Europe, 2013
2012
A Variability-Aware Robust Design Space Exploration Methodology for On-Chip Multiprocessors Subject to Application-Specific Constraints.
ACM Trans. Embed. Comput. Syst., 2012
OSCAR: An Optimization Methodology Exploiting Spatial Correlation in Multicore Design Spaces.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
Parallel paradigms and run-time management techniques for many-core architectures: the 2PARMA approach.
Proceedings of the 2012 Interconnection Network Architecture, 2012
Keynote: "Design space exploration and run-time resource management in the embedded multi-core era".
Proceedings of the IEEE 10th Symposium on Embedded Systems for Real-time Multimedia, 2012
Using multi-objective design space exploration to enable run-time resource management for reconfigurable architectures.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
An exploration methodology for a customizable OpenCL stereo-matching application targeted to an industrial multi-cluster architecture.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012
Evaluating Run-time Resource Management Policies for Multi-core Embedded Platforms with the EMME Evaluation Framework.
Proceedings of the ARCS 2012 Workshops, 28. Februar - 2. März 2012, München, Germany, 2012
2011
Linking run-time resource management of embedded multi-core platforms with automated design-time exploration.
IET Comput. Digit. Tech., 2011
Proceedings of the IEEE 9th Symposium on Application Specific Processors, 2011
Invited paper: Parallel programming and run-time resource management framework for many-core platforms: The 2PARMA approach.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011
Floorplanning-aware design space exploration for application-specific hierarchical networks on-chip.
Proceedings of the 4th International Workshop on Network on Chip Architectures, 2011
Proceedings of the Multi-objective Design Space Exploration of Multiprocessor SoC Architectures, 2011
Proceedings of the Multi-objective Design Space Exploration of Multiprocessor SoC Architectures, 2011
Proceedings of the Multi-objective Design Space Exploration of Multiprocessor SoC Architectures, 2011
Design Space Exploration for Run-Time Management of a Reconfigurable System for Video Streaming.
Proceedings of the Multi-objective Design Space Exploration of Multiprocessor SoC Architectures, 2011
Proceedings of the Multi-objective Design Space Exploration of Multiprocessor SoC Architectures, 2011
Proceedings of the Multi-objective Design Space Exploration of Multiprocessor SoC Architectures, 2011
2010
Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010
2PARMA: Parallel Paradigms and Run-Time Management Techniques for Many-Core Architectures.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-Core Architectures.
Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010
An industrial design space exploration framework for supporting run-time resource management on multi-core systems.
Proceedings of the Design, Automation and Test in Europe, 2010
Energy-performance design space exploration in SMT architectures exploiting selective load value predictions.
Proceedings of the Design, Automation and Test in Europe, 2010
A correlation-based design space exploration methodology for multi-processor systems-on-chip.
Proceedings of the 47th Design Automation Conference, 2010
Multicube Explorer: An Open Source Framework for Design Space Exploration of Chip Multi-Processors.
Proceedings of the ARCS '10, 2010
2009
ReSPIR: A Response Surface-Based Pareto Iterative Refinement for Application-Specific Design Space Exploration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
A design space exploration methodology supporting run-time resource management for multi-processor Systems-on-chip.
Proceedings of the IEEE 7th Symposium on Application Specific Processors, 2009
Multi-processor system-on-chip Design Space Exploration based on multi-level modeling techniques.
Proceedings of the 2009 International Conference on Embedded Computer Systems: Architectures, 2009
Proceedings of the Second International Workshop on Network on Chip Architectures, 2009
Meta-model Assisted Optimization for Design Space Exploration of Multi-Processor Systems-on-Chip.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009
Variability-aware robust design space exploration of chip multiprocessor architectures.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
An Efficient Design Space Exploration Methodology for On-Chip Multiprocessors Subject to Application-Specific Constraints.
Proceedings of the IEEE Symposium on Application Specific Processors, 2008
An efficient design space exploration methodology for multiprocessor SoC architectures based on response surface methods.
Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, 2008
Proceedings of the 6th IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, 2008
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008
2005
J. Embed. Comput., 2005
Low-power branch prediction techniques for VLIW architectures: a compiler-hints based approach.
Integr., 2005
Des. Autom. Embed. Syst., 2005
Proceedings of the International Symposium on Information Technology: Coding and Computing (ITCC 2005), 2005
2004
Proceedings of the Integrated Circuit and System Design, 2004
Power-aware branch prediction techniques: a compiler-hints based approach for VLIW processors.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004
Proceedings of the 2004 Design, 2004
Proceedings of the Ultra Low-Power Electronics and Design, 2004
2003
A Methodology for the Efficient Architectural Exploration of Energy-Delay Trade-offs for Embedded Systems.
Proceedings of the 2003 ACM Symposium on Applied Computing (SAC), 2003
A Flexible Framework for Fast Multi-objective Design Space Exploration of Embedded Systems.
Proceedings of the Integrated Circuit and System Design, 2003
About the performances of the Advanced Encryption Standard in embedded systems with cache memory.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003
Power-Performance System-Level Exploration of a MicroSPARC2-Based Embedded Architecture.
Proceedings of the 2003 Design, 2003
2002
IEEE Trans. Very Large Scale Integr. Syst., 2002
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002
Des. Autom. Embed. Syst., 2002
A Framework for Modeling and Estimating the Energy Dissipation of VLIW-Based Embedded Systems.
Des. Autom. Embed. Syst., 2002
An Instruction-Level Methodology for Power Estimation and Optimization of Embedded VLIW Cores.
Proceedings of the 2002 Design, 2002
Energy estimation and optimization of embedded VLIW processors based on instruction clustering.
Proceedings of the 39th Design Automation Conference, 2002
2001
An Agent-Based Approach to Full Interoperability and Allocation Transparency in Distributed File Systems.
Proceedings of the Mobile Agents for Telecommunication Applications, 2001
Fast system-level exploration of memory architectures driven by energy-delay metrics.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001
2000
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000
Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000