Gulay Yalcin

According to our database1, Gulay Yalcin
  • authored at least 23 papers between 2007 and 2017.
  • has a "Dijkstra number"2 of four.

Timeline

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On csauthors.net:

Bibliography

2017
Designing and Modelling Selective Replication for Fault-tolerant HPC Applications.
Proceedings of the 17th IEEE/ACM International Symposium on Cluster, 2017

2016
Exploring Energy Reduction in Future Technology Nodes via Voltage Scaling with Application to 10nm.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016

CRC-Based Memory Reliability for Task-Parallel HPC Applications.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium, 2016

Energy minimization at all layers of the data center: The ParaDIME project.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

A Runtime Heuristic to Selectively Replicate Tasks for Application-Specific Reliability Targets.
Proceedings of the 2016 IEEE International Conference on Cluster Computing, 2016

2015
ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy for data centers.
Microprocessors and Microsystems - Embedded Hardware Design, 2015

JSRAM: A Circuit-Level Technique for Trading-Off Robustness and Capacity in Cache Memories.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Transactional Memory for Reliability.
Proceedings of the Transactional Memory. Foundations, Algorithms, Tools, and Applications, 2015

2014
Exploiting Existing Comparators for Fine-Grained Low-Cost Error Detection.
TACO, 2014

Bit Impact Factor: Towards making fair vulnerability comparison.
Microprocessors and Microsystems - Embedded Hardware Design, 2014

Neighbor-cell assisted error correction for MLC NAND flash memories.
Proceedings of the ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems, 2014

Combining Error Detection and Transactional Memory for Energy-Efficient Computing below Safe Operation Margins.
Proceedings of the 22nd Euromicro International Conference on Parallel, 2014

Exploiting a fast and simple ECC for scaling supply voltage in level-1 caches.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

System-level power & energy estimation methodology and optimization techniques for CPU-GPU based mobile platforms.
Proceedings of the 12th IEEE Symposium on Embedded Systems for Real-time Multimedia, 2014

ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Flexicache: Highly Reliable and Low Power Cache under Supply Voltage Scaling.
Proceedings of the High Performance Computing - First HPCLATAM, 2014

2013
Circuit design of a novel adaptable and reliable L1 data cache.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

FaulTM: error detection and recovery using hardware transactional memory.
Proceedings of the Design, Automation and Test in Europe, 2013

Fault tolerance for multi-threaded applications by leveraging hardware transactional memory.
Proceedings of the Computing Frontiers Conference, 2013

2012
Flash correct-and-refresh: Retention-aware error management for increased flash memory lifetime.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

2011
FIMSIM: A fault injection infrastructure for microarchitectural simulators.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

SymptomTM: Symptom-Based Error Detection and Recovery Using Hardware Transactional Memory.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2007
Using Tag-Match Comparators for Detecting Soft Errors.
Computer Architecture Letters, 2007


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