Pablo Prieto

According to our database1, Pablo Prieto
  • authored at least 16 papers between 2007 and 2016.
  • has a "Dijkstra number"2 of four.



In proceedings 
PhD thesis 




AC-WAR: Architecting the Cache Hierarchy to Improve the Lifetime of a Non-Volatile Endurance-Limited Main Memory.
IEEE Trans. Parallel Distrib. Syst., 2016

Race-track testing of a torque vectoring algorithm on a motor-in-wheel car using a model-based methodology with a HiL and multibody simulator setup.
Proceedings of the 19th IEEE International Conference on Intelligent Transportation Systems, 2016

Energy minimization at all layers of the data center: The ParaDIME project.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Improving last level shared cache performance through mobile insertion policies (MIP).
Parallel Computing, 2015

ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy for data centers.
Microprocessors and Microsystems - Embedded Hardware Design, 2015

SARA-Coffee web server, a tool for the computation of RNA sequence and structure multiple alignments.
Nucleic Acids Research, 2014

CMP off-chip bandwidth scheduling guided by instruction criticality.
Proceedings of the International Conference on Supercomputing, 2013

Interaction of NoC Design and Coherence Protocol in 3D-Stacked CMPs.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

TOPAZ: An Open-Source Interconnection Network Simulator for Chip Multiprocessors and Supercomputers.
Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012

BIXBAR: A low cost solution to support dynamic link reconfiguration in networks on chip.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Multilevel Cache Modeling for Chip-Multiprocessor Systems.
Computer Architecture Letters, 2011

Spectrum Occupancy and Hidden Node Margins for Cognitive Radio Applications in the UHF Band.
Proceedings of the Mobile Multimedia Communications - 7th International ICST Conference, 2011

Design and implementation of a direct RF-to-digital UHF-TV multichannel transceiver.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

SP-NUCA: a cost effective dynamic non-uniform cache architecture.
SIGARCH Computer Architecture News, 2008

Design, Simulation and Implementation of a Channel Equalizer for DVB-T On-channel Repeaters.
Proceedings of the 3rd International Conference on Systems and Networks Communications, 2008

Rotary router: an efficient architecture for CMP interconnection networks.
Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007