Pablo Prieto

Orcid: 0000-0002-5818-1188

According to our database1, Pablo Prieto authored at least 28 papers between 2007 and 2023.

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Bibliography

2023
Digital twin based simulation platform for heavy duty hybrid electric vehicles.
Proceedings of the 97th IEEE Vehicular Technology Conference, 2023

Fuzzy Logic Strategy for Traction Control in Parallel Hybrid Vehicles.
Proceedings of the 25th IEEE International Conference on Intelligent Transportation Systems, 2023

Performance Characterization of Popular DNN Models on Out-of-Order CPUs.
Proceedings of the 32nd International Conference on Parallel Architectures and Compilation Techniques, 2023

2022
Top-Down Performance Profiling on NVIDIA's GPUs.
Proceedings of the 2022 IEEE International Parallel and Distributed Processing Symposium, 2022

2021
Fast, Accurate Processor Evaluation Through Heterogeneous, Sample-Based Benchmarking.
IEEE Trans. Parallel Distributed Syst., 2021

2020
The gem5 Simulator: Version 20.0+.
CoRR, 2020

SPECcast: A Methodology for Fast Performance Evaluation with SPEC CPU 2017 Multiprogrammed Workloads.
Proceedings of the ICPP 2020: 49th International Conference on Parallel Processing, 2020

2019
Accuracy vs. Computational Cost Tradeoff in Distributed Computer System Simulation.
CoRR, 2019

Architecting Racetrack Memory Preshift through Pattern-Based Prediction Mechanisms.
Proceedings of the 2019 IEEE International Parallel and Distributed Processing Symposium, 2019

Geo-Fence Based Route Tracking Diagnosis Strategy for Energy Prediction Strategies Applied to EV.
Proceedings of the IECON 2019, 2019

Modelling and Validation of Full Vehicle Model based on a Novel Multibody Formulation.
Proceedings of the IECON 2019, 2019

2018
Memory Hierarchy Characterization of NoSQL Applications through Full-System Simulation.
IEEE Trans. Parallel Distributed Syst., 2018

2016
AC-WAR: Architecting the Cache Hierarchy to Improve the Lifetime of a Non-Volatile Endurance-Limited Main Memory.
IEEE Trans. Parallel Distributed Syst., 2016

Race-track testing of a torque vectoring algorithm on a motor-in-wheel car using a model-based methodology with a HiL and multibody simulator setup.
Proceedings of the 19th IEEE International Conference on Intelligent Transportation Systems, 2016

Energy minimization at all layers of the data center: The ParaDIME project.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Improving last level shared cache performance through mobile insertion policies (MIP).
Parallel Comput., 2015

ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy for data centers.
Microprocess. Microsystems, 2015

2014
SARA-Coffee web server, a tool for the computation of RNA sequence and structure multiple alignments.
Nucleic Acids Res., 2014

2013
CMP off-chip bandwidth scheduling guided by instruction criticality.
Proceedings of the International Conference on Supercomputing, 2013

Interaction of NoC Design and Coherence Protocol in 3D-Stacked CMPs.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012
TOPAZ: An Open-Source Interconnection Network Simulator for Chip Multiprocessors and Supercomputers.
Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012

BIXBAR: A low cost solution to support dynamic link reconfiguration in networks on chip.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

2011
Multilevel Cache Modeling for Chip-Multiprocessor Systems.
IEEE Comput. Archit. Lett., 2011

Spectrum Occupancy and Hidden Node Margins for Cognitive Radio Applications in the UHF Band.
Proceedings of the Mobile Multimedia Communications - 7th International ICST Conference, 2011

2010
Design and implementation of a direct RF-to-digital UHF-TV multichannel transceiver.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2008
SP-NUCA: a cost effective dynamic non-uniform cache architecture.
SIGARCH Comput. Archit. News, 2008

Design, Simulation and Implementation of a Channel Equalizer for DVB-T On-channel Repeaters.
Proceedings of the 3rd International Conference on Systems and Networks Communications, 2008

2007
Rotary router: an efficient architecture for CMP interconnection networks.
Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007


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