Santhosh Kumar Rethinagiri

According to our database1, Santhosh Kumar Rethinagiri authored at least 22 papers between 2011 and 2016.

Collaborative distances:



In proceedings 
PhD thesis 




Exploring Energy Reduction in Future Technology Nodes via Voltage Scaling with Application to 10nm.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016

Energy minimization at all layers of the data center: The ParaDIME project.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Scalable row-based parallel H.264 decoder on embedded multicore processors.
Signal, Image and Video Processing, 2015

ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy for data centers.
Microprocessors and Microsystems - Embedded Hardware Design, 2015

FAcET: Fast and accurate power/energy estimation tool for CPU-GPU platforms at architectural-level.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

VPM: Virtual power meter tool for low-power many-core/heterogeneous data center prototypes.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Trigeneous Platforms for Energy Efficient Computing of HPC Applications.
Proceedings of the 22nd IEEE International Conference on High Performance Computing, 2015

Heterogeneous Platform to Accelerate Compute Intensive Applications.
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

An energy efficient hybrid FPGA-GPU based embedded platform to accelerate face recognition application.
Proceedings of the 2015 IEEE Symposium in Low-Power and High-Speed Chips, 2015

DESSERT: DESign Space ExploRation Tool based on power and energy at System-Level.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

System-level power estimation tool for embedded processor based platforms.
Proceedings of the 2014 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2014

VPPET: Virtual platform power and energy estimation tool for heterogeneous MPSoC based FPGA platforms.
Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014

System-Level Power and Energy Estimation Methodology for Open Multimedia Applications Platforms.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

PETS: Power and energy estimation tool at system-level.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Power estimation tool for system on programmable chip based platforms (abstract only).
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

APMC: advanced pattern based memory controller (abstract only).
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

System-level power & energy estimation methodology and optimization techniques for CPU-GPU based mobile platforms.
Proceedings of the 12th IEEE Symposium on Embedded Systems for Real-time Multimedia, 2014

ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

An efficient power estimation methodology for complex RISC processor-based platforms.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

A system level power consumption estimation for MPSoC.
Proceedings of the 2011 International Symposium on System on Chip, 2011

Hybrid system level power consumption estimation for FPGA-based MPSoC.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Fast and accurate hybrid power estimation methodology for embedded systems.
Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011