Cristiano Santos

According to our database1, Cristiano Santos authored at least 23 papers between 2003 and 2021.

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Bibliography

2021
Block-Based Inter-Frame Prediction For Dynamic Point Cloud Compression.
Proceedings of the 2021 IEEE International Conference on Image Processing, 2021

2017
A 4 × 4 × 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links.
IEEE J. Solid State Circuits, 2017

Rate and Complexity-Aware Coding Scheme for Fixed-Camera Videos Based on Region-of-Interest Detection.
Proceedings of the 23rd Brazillian Symposium on Multimedia and the Web, 2017

Objective and Subjective Video Quality Assessment in Mobile Devices for Low-Complexity H.264/AVC Codecs.
Proceedings of the 23rd Brazillian Symposium on Multimedia and the Web, 2017

Transistor Temperature Deviation Analysis in Monolithic 3D Standard Cells.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

2016
Experimental Insights Into Thermal Dissipation in TSV-Based 3-D Integrated Circuits.
IEEE Des. Test, 2016

8.1 A 4×4×2 homogeneous scalable 3D network-on-chip circuit with 326MFlit/s 0.66pJ/b robust and fault-tolerant asynchronous 3D links.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016


Thermal performance of CoolCube™ monolithic and TSV-based 3D integration processes.
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

2015
Thermal Aspects and High-Level Explorations of 3D Stacked DRAMs.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Retention time measurements and modelling of bit error rates of WIDE I/O DRAM in MPSoCs.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Graphite-based heat spreaders for hotspot mitigation in 3D ICs.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

2014
Thermal impact of 3D stacking and die thickness: Analysis and characterization of a memory-on-logic 3D circuit.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

Thermal modeling methodology for efficient system-level thermal analysis.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

Thermal performance of 3D ICs: Analysis and alternatives.
Proceedings of the 2014 International 3D Systems Integration Conference, 2014

Using TSVs for thermal mitigation in 3D circuits: Wish and truth.
Proceedings of the 2014 International 3D Systems Integration Conference, 2014

2013
System-level thermal modeling for 3D circuits: Characterization with a 65nm memory-on-logic circuit.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2012
Multi-bit flip-flop usage impact on physical synthesis.
Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012

2007
Efficient timing closure with a transistor level design flow.
Proceedings of the IFIP VLSI-SoC 2007, 2007

2006
A New Transistor-Level Layout Generation Strategy for Static CMOS Circuits.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005
A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier Architectures.
Proceedings of the VLSI-SoC: From Systems To Silicon, 2005

Incremental timing optimization for automatic layout generation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2003
A Transistor Sizing Method Applied to an Automatic Layout Generation Tool.
Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003


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