Hiromasa Takahashi

According to our database, Hiromasa Takahashi authored at least 13 papers between 1990 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

Conducting an Experiment at Multiple Sites with Small Subject Pools: How is Raven Score Effective as a Covariate?

Kazuhito Ogawa, Yusuke Osaki, Tetsuya Kawamura, Hiromasa Takahashi, Satoshi Taguchi, Yoichiro Fujii, Kengo Kurosaka, Kohei Iyori, Naoki Watanabe

Proceedings of the IEEE International Conference on Big Data, 2023

2022

Cheating, Trust and Social Norms: Data from Germany, Vietnam, China, Taiwan, and Japan.

Toan Luu Duc Huynh, Marc Oliver Rieger, Mei Wang, David Berens, Duy-Linh Bui, Hung-Ling Chen, Tobias Peter Emering, Sen Geng, Yang Liu-Gerhards, Thomas Neumann, Thanh Dac Nguyen, Thong Trung Nguyen, Diefeng Peng, Thuy Chung Phan, Denis Reinhardt, Junyi Shen, Hiromasa Takahashi, Bodo Vogt

Data, 2022

2020

Can players avoid the tragedy of the commons in a joint debt game?

Hiromasa Takahashi, Toru Takemoto, Akihiro Suzuki

Int. J. Game Theory, 2020

2011

A vector coprocessor architecture for embedded systems.

Yi Ge, Yoshimasa Takebe, Masahiko Toichi, Makoto Mouri, Makiko Ito, Yoshio Hirose, Hiromasa Takahashi

Proceedings of the International SoC Design Conference, 2011

2010

A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and '1'/'0' Dual-Array Equalized Reference Scheme.

Riichiro Takemura, Takayuki Kawahara, Katsuya Miura, Hiroyuki Yamamoto, Jun Hayakawa, Nozomu Matsuzaki, Kazuo Ono, Michihiko Yamanouchi, Kenchi Ito, Hiromasa Takahashi, Shoji Ikeda, Haruhiro Hasegawa, Hideyuki Matsuoka, Hideo Ohno

IEEE J. Solid State Circuits, 2010

2008

2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read.

Takayuki Kawahara, Riichiro Takemura, Katsuya Miura, Jun Hayakawa, Shoji Ikeda, Young Min Lee, Ryutaro Sasaki, Yasushi Goto, Kenchi Ito, Toshiyasu Meguro, Fumihiro Matsukura, Hiromasa Takahashi, Hideyuki Matsuoka, Hideo Ohno

IEEE J. Solid State Circuits, 2008

2007

2Mb Spin-Transfer Torque RAM (SPRAM) with Bit-by-Bit Bidirectional Current Write and Parallelizing-Direction Current Read.

Takayuki Kawahara, Riichiro Takemura, Katsuya Miura, Jun Hayakawa, Shoji Ikeda, Young Min Lee, Ryutaro Sasaki, Yasushi Goto, Kenchi Ito, Toshiyasu Meguro, Fumihiro Matsukura, Hiromasa Takahashi, Hideyuki Matsuoka, Hideo Ohno

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

SPRAM (SPin-transfer torque RAM) design and its impact on digital systems.

Takayuki Kawahara, Riichiro Takemura, Hiromasa Takahashi, Hideo Ohno

Proceedings of the 14th IEEE International Conference on Electronics, 2007

2004

Autonomous decentralized control for formation of multiple mobile robots considering ability of robot.

Hiromasa Takahashi, Hiroaki Nishi, Kouhei Ohnishi

IEEE Trans. Ind. Electron., 2004

1999

A 2.5-GFLOPS, 6.5 million polygons per second, four-way VLIW geometry processor with SIMD instructions and a software bypass mechanism.

Hajime Kubosawa, Naoshi Higaki, Satoshi Ando, Hiromasa Takahashi, Yoshimi Asada, Hideaki Anbutsu, Tomio Sato, Masato Sakate, Atsuhiro Suga, Michihide Kimura, Hideo Miyake, Hiroshi Okano, Akira Asato, Yasunori Kimura, Hiroshi Nakayama, Masayoshi Kimoto, Katsuji Hirochi, Hideki Saito, Norio Kaido, Yukihiro Nakagawa, Toshio Shimada

IEEE J. Solid State Circuits, 1999

1998

A 1.2-W, 2.16-GOPS/720-MFLOPS embedded superscalar microprocessor for multimedia applications.

Hajime Kubosawa, Hiromasa Takahashi, Satoshi Ando, Yoshimi Asada, Akira Asato, Atsuhiro Suga, Michihide Kimura, Naoshi Higaki, Hideo Miyake, Tomio Sato, Hideaki Anbutsu, Toshitaka Tsuda, Tetsuo Yoshimura, Isao Amano, Mutsuaki Kai, Shin Mitarai

IEEE J. Solid State Circuits, 1998

1993

The μVP 64-bit vector coprocessor: a new implementation of high-performance numerical computation.

Makoto Awaga, Hiromasa Takahashi

IEEE Micro, 1993

1990

A 64-bit floating-point processing unit with a horizontal instruction code for parallel operations.

Akira Katsuno, Hiromasa Takahashi, Hajime Kubosawa, Tomio Sato, Atsuhiro Suga, Gensuke Goto

Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990