Hyunui Lee

According to our database, Hyunui Lee authored at least 5 papers between 2013 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2017

A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution.

Kyomin Sohn, Won-Joo Yun, Reum Oh, Chi-Sung Oh, Seong-Young Seo, Min-Sang Park, Dong-Hak Shin, Won-Chang Jung, Sang-Hoon Shin, Je-Min Ryu, Hye-Seung Yu, Jae-Hun Jung, Hyunui Lee, Seok-Yong Kang, Young-Soo Sohn, Jung-Hwan Choi, Yong-Cheol Bae, Seong-Jin Jang, Gyo-Young Jin

IEEE J. Solid State Circuits, 2017

2016

Design of non-contact 2Gb/s I/O test methods for high bandwidth memory (HBM).

Hyunui Lee, Sukyong Kang, Hye-Seung Yu, Won-Joo Yun, Jae-Hun Jung, Sungoh Ahn, Wang-Soo Kim, Beomyong Kil, Yoo-Chang Sung, Sang-Hoon Shin, Yong-Sik Park, Yong-Hwan Kim, Kyung-Woo Nam, Indal Song, Kyomin Sohn, Yong-Cheol Bae, Jung-Hwan Choi, Seong-Jin Jang, Gyo-Young Jin

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2013

A 12-bit Interpolated Pipeline ADC Using Body Voltage Controlled Amplifier.

Hyunui Lee, Masaya Miyahara, Akira Matsuzawa

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

Design of Interpolated Pipeline ADC Using Low-Gain Open-Loop Amplifiers.

Hyunui Lee, Masaya Miyahara, Akira Matsuzawa

IEICE Trans. Electron., 2013

A 6 bit, 7 mW, 700 MS/s Subranging ADC Using CDAC and Gate-Weighted Interpolation.

Hyunui Lee, Yusuke Asada, Masaya Miyahara, Akira Matsuzawa

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013