Hyunui Lee

According to our database1, Hyunui Lee authored at least 5 papers between 2013 and 2017.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2017
A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution.
IEEE J. Solid State Circuits, 2017

2016
Design of non-contact 2Gb/s I/O test methods for high bandwidth memory (HBM).
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2013
A 12-bit Interpolated Pipeline ADC Using Body Voltage Controlled Amplifier.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

Design of Interpolated Pipeline ADC Using Low-Gain Open-Loop Amplifiers.
IEICE Trans. Electron., 2013

A 6 bit, 7 mW, 700 MS/s Subranging ADC Using CDAC and Gate-Weighted Interpolation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013


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