Reum Oh

According to our database1, Reum Oh authored at least 7 papers between 2013 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2021
25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3<sup>rd</sup>-Generation 10nm DRAM.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2018
3D-Xpath: high-density managed DRAM architecture with cost-effective alternative paths for memory transactions.
Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques, 2018

2017
A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution.
IEEE J. Solid State Circuits, 2017

2016
18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2014
Design technologies for a 1.2V 2.4Gb/s/pin high capacity DDR4 SDRAM with TSVs.
Proceedings of the Symposium on VLSI Circuits, 2014

2013
Design and verification of an all-digital on-chip process variation sensor.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

All digital on-chip temperature sensor using dual ring oscillators.
Proceedings of the 20th IEEE International Conference on Electronics, 2013


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