Gyo-Young Jin
According to our database1,
Gyo-Young Jin
authored at least 13 papers
between 1991 and 2019.
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Bibliography
2019
A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking.
IEEE J. Solid State Circuits, 2019
2017
A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution.
IEEE J. Solid State Circuits, 2017
23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
23.4 An extremely low-standby-power 3.733Gb/s/pin 2Gb LPDDR4 SDRAM for wearable devices.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017
2016
18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
2015
A 6.4Gb/s/pin at sub-1V supply voltage TX-interleaving technique for mobile DRAM interface.
Proceedings of the Symposium on VLSI Circuits, 2015
The classification methodology of chip quality using canonical correlation analysis-based variable selection on chip level data.
Proceedings of the 2015 IEEE International Conference on Industrial Engineering and Engineering Management, 2015
2012
Novel Deep Trench Buried-Body-Contact (DBBC) of 4F<sup>2</sup> cell for sub 30nm DRAM technology.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012
2010
A 31 ns Random Cycle VCAT-Based 4F <sup>2</sup> DRAM With Manufacturability and Enhanced Cell Efficiency.
IEEE J. Solid State Circuits, 2010
1991
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991