Hye-Seung Yu

According to our database1, Hye-Seung Yu authored at least 4 papers between 2005 and 2017.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2017
A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution.
IEEE J. Solid State Circuits, 2017

2016
18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

Design of non-contact 2Gb/s I/O test methods for high bandwidth memory (HBM).
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2005
An advanced bit-line clamping scheme in magnetic RAM for wide sensing margin.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005


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